ECL 10000 SERIE Search Results

8 PIN DIL

Contextual Info: FEATURES PAGE NO. 4 6 7 General Delav Line Information Standard Test Circuits Pulse Waveforms PAGE NO. SERIES AND FEATURES P A S S I V E D E L A Y LINES Series DIP14, DIP16, DIPG14, DIPG14 - 14 Pin DIP & SMD, 10 Taps Series JSA, JSB - Surface Mountinq J Leads, 10 Taps

10GHz clock oscillator

Abstract: TD6380 TD6380N TD6380P TD6380Z TD6381N TD6381P TD6381Z TD6382N TD6382P
Contextual Info: TD6380,81,82P/N/Z TO SH IBA TO SHIBA BIPO LAR DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TD6380P, TD6380N, TD6380Z, TD6381P, TD6381N, TD6381Z, TD6382P, TD6382N, TD6382Z FREQUENCY SYNTHESIZER FOR TV /CA TV A series of TD6380~6382 are a single-chip frequency

L42n

Abstract: HM3500 adb 630 L43n "alu 4 bit" ECL IC NAND L44N PT06-16-8P-S/transistor 03e
Contextual Info: H0NEYWE1_I_/SS ELEK-, MIL [13 I>e | 4551872 DD00212 D • “ H o n eyw e ll r - n - ll'O HM3500, hvmioooo, HE12000 Preliminary ADVANCED DIGITAL BIPOLAR GATE ARRAY FAMILY FAMILY FEATURES • Broad Performance Optimized Family Allows Flexible System Partitioning:

8891

Abstract: toshiba 8891 TD6380 TD6380N TD6380P TD6380Z TD6381N TD6381P TD6381Z TD6382N
Contextual Info: TOSHIBA TD6380,81,82P/N/Z TO SH IBA BIPO LAR D IG ITAL INTEGRATED CIRCUIT SILICON M ONOLITHIC TD6380P, TD6380N, TD6380Z, TD6381P, TD6381N, TD6381Z, TD6382P, TD6382N, TD6382Z FREQUENCY SYNTHESIZER FOR TV/CATV A series o f TD 6380~6382 are a single-chip frequency

Contextual Info: TD6380,81,82P/N/Z T O SH IB A TOSHIBA BIPOLAR DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TD6380P, TD6380N, TD6380Z, TD6381P, TD6381N, TD6381Z, TD6382P, TD6382N, TD6382Z FREQUENCY SYNTHESIZER FOR TV /CATV A series of TD6380~6382 are a single-chip frequency

Contextual Info: INTEGRATED TO SH IB A TOSHIBA BIPOLAR DIGITAL INTEGRATED CIRCUIT TD6380P, TD6380N, TD6380Z TD6381P, TD6381N, TD6381Z TD6382P, TD6382N, TD6382Z SILICON MONOLITHIC CIRCUIT t e c h n ic a l data FREQUENCY SYNTHESIZER FOR TV/CATV A series of TD6380~6382 are a single-chip frequency

MIL-HDBK-217

Contextual Info: 9810A Rev. B NEL CRYSTAL CLOCK OSCILLATORS SJ/HJ-X8XX series clock oscillators Reliability Calculations Based on MIL-HDBK-217 F 1 . .01 2.2 θjc 1 . .0035 .15 1 . .025 .64 1 . .025 .64 Silicon,epoxy,alumina,and alumina 0.05.0.05 θjc = 42.402 junction to case thermal resistance

ASTM-F-1892

Abstract: 38510R75001 ASTM-F1892 54AC14 MDS 54AC00 seu 54AC00 Fairchild 54ac14 54ACTQ574 54AC14 seu 54AC08
Contextual Info: N RADIATION OWNER’S MANUAL Logic Table of Contents Page Glossary of Logic-Specific Terms Radiation Results – Logic Summary FACT AC/ACT Advanced CMOS Logic FACT Quiet Series™ (ACQ/ACTQ) FACT FCT F100K 300 Series ECL Total Dose Degradation of the Device’s Switchpoint

ps5120

Contextual Info: MC100EP196 3.3V ECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture to the EP195 with the added feature of further tuneability in

Contextual Info: MC100EP196 3.3V ECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar

E196

Abstract: MC100 MC100EP196
Contextual Info: MC100EP196 3.3V ECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar

PS-4480 B

Abstract: E196 MC100 MC100EP196 ps 5040 750MV
Contextual Info: MC100EP196 3.3V ECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture to the EP195 with the added feature of further tuneability in

E196

Abstract: MC100 MC100EP196 PS2022
Contextual Info: MC100EP196 3.3V ECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar

ic 4440 circuit diagram

Abstract: PS-4480 B PS-4480 ic 4440 pin diagram of ic 4440 E196 MC100 MC100EP196 gd d9 ECL 10000
Contextual Info: MC100EP196 3.3V ECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar

PS-4480 B

Contextual Info: MC100EP196 3.3V ECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture to the EP195 with the added feature of further tuneability in

gk25

Abstract: kd35 vectron 271 231500 vectron Co CO-272
Contextual Info: VCXOs, TC/VCXOs.to 600 MHz TEMPERATURE COMPENSATED TC/VCXOs CO-351_ CO-352 BASIC VCXOs CO-271 CENTER FREQUENCY CO-275 CO-275: 23.1-100 MHz C0-275H: 100.1-600 MHz (Models differ in pin pattern) to 23 MHz M O DULATION C H ARACTERISTICS to 20 Mhz

MC100EP195

Abstract: MC100EP195FA MC100EP195FAR2 MC10EP195 MC10EP195FA MC10EP195FAR2 marking EE
Contextual Info: MC10EP195, MC100EP195 3.3V ECL Programmable Delay Chip The MC10/100EP195 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and

E196

Abstract: MC100 MC100EP196
Contextual Info: MC100EP196 3.3V ECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture to the EP195 with the added feature of further tuneability in

Contextual Info: MC100EP196 3.3V ECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar

PS-4480 B

Abstract: ic 4440 circuit diagram E196 MC100 MC100EP196
Contextual Info: MC100EP196 3.3V ECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture to the EP195 with the added feature of further tuneability in

Contextual Info: MC100EP196A 3.3 V ECL Programmable Delay Chip With FTUNE The MC100EP196A is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture to the EP195 with the added feature of further

Contextual Info: MC10EP195, MC100EP195 3.3V / 5VĄECL Programmable Delay Chip The MC10/100EP195 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and

L 3005 TRANSISTOR

Contextual Info: TEMPERATURE-SENSITIVE RESISTORS INTRODUCTION ECl Temperature-Sensitive Resistors have been developed to be an improved cost/perform ance alternative fo r temperaturerelated fields. On a high grade ceramic body, a thermo-sensitive film o f nickel alloy is deposited. Contact caps o f special alloy are then

180 ohm resistor

Abstract: 14p marking resistor 270 ohm resistor 4700 ohm 470 ohm resistor Tektronix 11802 270 ohm resistor resistance 220 ohm resistor 330 Ohm DATA SHEET resistor 39 ohm
Contextual Info: Surface Mount Series 752 Ohms EIA Code 10 12 15 18 22 27 33 39 47 51 56 68 82 100 110 120 150 180 200 220 270 330 390 470 510 560 680 820 1000 1100 1200 1500 1800 2000 2200 2700 Bussed DRT Schematic 1 N N-1 N/2 + 1 1 2 N/2 Single Row Termination (SRT) PAD #1 MARK