E1-28 TRANSFORMER Search Results
E1-28 TRANSFORMER Result Highlights (5)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
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| IXF1002EDT-G |
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IXF1002 - Dual Port Gigabit Ethernet Controller |
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| IXF1002EDT |
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IXF1002 - Dual Port Gigabit Ethernet Controller |
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| AM79C961AVI |
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Full Duplex 10/100 MBPS ETHERNET Controller for PCI Local Bus, PCNET- ISA II jumperless |
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| IXF1002ED |
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IXF1002ED - Dual Port Gigabit Ethernet Controller |
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| IXF1002ED-G |
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IXF1002ED - Dual Port Gigabit Ethernet Controller |
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E1-28 TRANSFORMER Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
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Contextual Info: Hardware Manual, P1.0.1, October 2005 INTEGRATED 28-CHANNEL T1/E1 LIU/FRAMER, VT/TU MAPPER AND M13 MULTIPLEXER XRT86SH328 Network & Transmission Products XRT86SH328 Hardware Manual GENERAL DESCRIPTION 1 GENERAL DESCRIPTION • Supports 21 E1 mapped as Asynchronous VT2 into an |
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28-CHANNEL XRT86SH328 XRT86SH328 | |
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Contextual Info: XRT83L38 PRELIMINARY OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR OCTOBER 2003 REV. P1.3.6 GENERAL DESCRIPTION The XRT83L38 is a fully integrated Octal eight channel long-haul and short-haul line interface unit for T1 (1.544Mbps) 100Ω, E1 (2.048Mbps) 75Ω or |
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XRT83L38 XRT83L38 544Mbps) 048Mbps) 772kHz 1024kHz | |
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Contextual Info: xr XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT JULY 2005 REV. 1.0.2 GENERAL DESCRIPTION Additional features include RLOS, a 16-bit LCV counter for each channel, AIS, QRSS/PRBS generation/detection, TAOS, DMO, and diagnostic loopback modes. |
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XRT83SH314 14-CHANNEL XRT83SH314 | |
8051 example programsContextual Info: áç XRT83L38 PRELIMINARY OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR SEPTEMBER 2001 REV. P1.1.1 GENERAL DESCRIPTION The XRT83L38 is a fully integrated Octal eight channels long-haul and short-haul line interface unit for T1(1.544Mbps) 100Ω, E1(2.048Mbps) 75Ω or 120Ω |
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XRT83L38 XRT83L38 544Mbps) 048Mbps) 772kHz 1024kHz 8051 example programs | |
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Contextual Info: áç XRT83SL34 PRELIMINARY QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR JANUARY 2003 REV. P1.0.6 GENERAL DESCRIPTION The XRT83SL34 is a fully integrated Quad four channel short-haul line interface unit for T1 (1.544Mbps) 100Ω, E1 (2.048Mbps) 75Ω or 120Ω, or |
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XRT83SL34 XRT83SL34 544Mbps) 048Mbps) | |
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Contextual Info: XRT86VL30 T1/E1/J1 BITS ELEMENT - HARDWARE MANUAL AUGUST 2008 REV. 1.0.2 GENERAL DESCRIPTION The XRT86VL30 is a single channel T1/E1/J1 BITS clock recovery element and framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . |
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XRT86VL30 XRT86VL30 | |
dmo 365 r
Abstract: dmo 365
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XRT83VSH316 16-CHANNEL XRT83VSH316 dmo 365 r dmo 365 | |
Intel 8081
Abstract: intel 80c188 users manual rur 450
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XRT82L24A XRT82L24A 048Mbps) 31-Jul-09 XRT82L24AIV-F LQFP100 XRT82L24AIV LQFP100 Intel 8081 intel 80c188 users manual rur 450 | |
IRF540S
Abstract: A1HB
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IRF540S, SiHF540S 2002/95/EC O-263) 2011/65/EU 2002/95/EC. 2002/95/EC 2011/65/EU. 12-Mar-12 IRF540S A1HB | |
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Contextual Info: xr XRT86VL32 PRELIMINARY DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION JULY 2005 REV. P1.0.5 GENERAL DESCRIPTION The XRT86VL32 is a two-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, |
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XRT86VL32 XRT86VL32 | |
IRFP250 applicationContextual Info: IRFP250, SiHFP250 Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS V • • • • • • • 200 RDS(on) (Ω) VGS = 10 V 0.085 Qg (Max.) (nC) 140 Qgs (nC) 28 Qgd (nC) 74 Configuration Single D S COMPLIANT Third generation Power MOSFETs from Vishay provide the |
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IRFP250, SiHFP250 2002/95/EC O-220AB 2011/65/EU 2002/95/EC. 2002/95/EC 2011/65/EU. 12-Mar-12 IRFP250 application | |
type j thermocouple
Abstract: design the 4-20mA transmitter for a thermistor using XTR
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XTR101 SBOS146A 4-20mA XTR101 4-20mA, type j thermocouple design the 4-20mA transmitter for a thermistor using XTR | |
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Contextual Info: XTR101 SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004 Precision, Low Drift 4-20mA TWO-WIRE TRANSMITTER FEATURES D INSTRUMENTATION AMPLIFIER INPUT: − Low Offset Voltage, 30µV max − Low Voltage Drift, 0.75µV/°C max − Low Nonlinearity, 0.01% max D TRUE TWO-WIRE OPERATION: |
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XTR101 SBOS146A 4-20mA XTR101 4-20mA, | |
AD9709
Abstract: ISL5629 ISL5629EVAL1 ISL5629IN
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ISL5629 FN6018 ISL5629 233mW 130MSPS ISL5x61 ISL5x29 14-bit AD9709 ISL5629EVAL1 ISL5629IN | |
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P109Contextual Info: XRT86VL38 PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION JUNE 2006 REV. P1.0.9 GENERAL DESCRIPTION The XRT86VL38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, |
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XRT86VL38 XRT86VL38 P109 | |
SiHB12N60E
Abstract: s1206
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SiHB12N60E 2011/65/EU 2002/95/EC. 2002/95/EC 2011/65/EU. 12-Mar-12 s1206 | |
IRF630STRLPBFContextual Info: IRF630S, SiHF630S Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS V • Halogen-free According to IEC 61249-2-21 Definition • Surface Mount • Available in Tape and Reel • Dynamic dV/dt Rating • Repetitive Avalanche Rated • Fast Switching |
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IRF630S, SiHF630S 2002/95/EC O-263) 2011/65/EU 2002/95/EC. 2002/95/EC 2011/65/EU. 12-Mar-12 IRF630STRLPBF | |
current fed push pull topologyContextual Info: UC1827-1, UC1827-2 UC2827-1, UC2827-2 UC3827-1, UC3827-2 www.ti.com SLUS365A – APRIL 1999 – REVISED AUGUST 2005 BUCK CURRENT/VOLTAGE FED PUSH-PULL PWM CONTROLLERS FEATURES • • • • • • • • DESCRIPTION Ideal for Multiple Output and/or High |
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UC1827-1, UC1827-2 UC2827-1, UC2827-2 UC3827-1, UC3827-2 SLUS365A UC3827-1 UC3827-2 current fed push pull topology | |
piezo transformer driver
Abstract: lumi drive inverter 220V LED Bulb circuit diagram INVERTER FOR EL PANEL electroluminescent display 1N4148 SP4501
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SP4501 200VP-P SP4501 14-Pin SP4501NEB piezo transformer driver lumi drive inverter 220V LED Bulb circuit diagram INVERTER FOR EL PANEL electroluminescent display 1N4148 | |
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Contextual Info: intJ 82C501AD ETHERNET SERIAL INTERFACE CHMOS Replacement for Intel 82C501, 82501, or SEEQ 8023A Manchester Encoding/Decoding and Receive Clock Recovery Conforms to IEEE 802.3 10BASE5 Ethernet and 10BASE2 (Cheapernet) Specifications 10-MHz Transmit Clock Generator |
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82C501AD 82C501, 10BASE5 10BASE2 10-MHz 10-Mb/s 82C501AD 10BASE5 10BAody | |
EL2470CS-T7
Abstract: EL2170 EL2170CN EL2170CS EL2176 EL2270 EL2276 EL2470 sot-23 5pin h2
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EL2170, EL2270, EL2470 70MHz/1mA EL2470 70MHz EL2270 EL2470CS-T7 EL2170 EL2170CN EL2170CS EL2176 EL2276 sot-23 5pin h2 | |
PSL 26
Abstract: AES17-1991 CS5334 CS5334-KS CS5335 CS5335-KS
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CS5334 CS5335 20-Bit, CS5334 CS5335 20-bit PSL 26 AES17-1991 CS5334-KS CS5335-KS | |
P-8CM
Abstract: IC P605 8 pin DIODE P31A "triac protection" overcurrent MOV surge protection circuit diagram p31b DIODE P31B Teccor P0080SC MC marking code diode s4 do-214 P3100EB
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E133083 E191008 O-220 P-8CM IC P605 8 pin DIODE P31A "triac protection" overcurrent MOV surge protection circuit diagram p31b DIODE P31B Teccor P0080SC MC marking code diode s4 do-214 P3100EB | |
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Contextual Info: intei 1.0 Networking Silicon — 82555 Introduction The 82555 is a highly integrated, physical layer interface solution designed for 10 and 100 Mbps Ethernet systems based on the IEEE 10BASE-T and 100BASE-TX specifications. 100BASE-TX is an IEEE 802.3 physical layer specification for use over two pairs of Category 5 unshielded twisted |
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10BASE-T 100BASE-TX 10BASE-T | |