DSC67 Search Results

82V3288

Abstract: BC208 transistor GR-1244-CORE GR-253-CORE IDT82V3288
Contextual Info: WAN PLL IDT82V3288 Version 2 June 22, 2006 6024 Silver Creek Valley Road, San Jose, CA 95138 Telephone: 800 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775 Printed in U.S.A. 2006 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry

CSR 8510

Abstract: CSR 8510 a10 CSR 8510 v4 80KSBR200 v8 doorbell wireless doorbell 813 doorbell circuit working ADS1118 2322 156 philips doorbell
Contextual Info: Advanced Datasheet 80KSBR200 sRIO SERIAL BUFFER FLOW-CONTROL DEVICE Device Overview ◆ The IDT80KSBR200 is a high speed Serial Buffer SerB that can connect to any Serial RapidIO compliant interface. This device is built to work with any sRIO device and especially with the IDT Pre-Processing

DOT96

Contextual Info: IDTCV146 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE IDTCV146 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR FEATURES: DESCRIPTION: • One high precision PLL for CPU, with SSC and N programmable • One high precision PLL for SRC/PCI/SATA, SSC and N programmable

CK410M

Abstract: CK409 CK410B DB400
Contextual Info: IDTCV143 1-TO-4 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE 1-TO-4 DIFFERENTIAL CLOCK BUFFER DESCRIPTION: FEATURES: • • • • • • • IDTCV143 The CV143 differential buffer is compliant with Intel DB400 specifications. It is intended to distribute the SRC serial reference clock as a companion chip

70P3337

Abstract: 70P3307
Contextual Info: PRELIMINARY DATASHEET IDT70P3307 IDT70P3337 1024K/512K x18 SYNCHRONOUS DUAL QDR-IITM Features ◆ 18Mb Density 1024K x 18 – Also available 9Mb Density (512K x 18) QDR-II x 18 Burst-of-2 Interface – Commercial: 233MHz, 250MHz Separate, Independent Read and Write Data Ports

Contextual Info: IDT5T93GL02 2.5V LVDS 1:2 GLITCHLESS CLOCK BUFFER TERABUFFER II INDUSTRIAL TEMPERATURE RANGE 2.5V LVDS 1:2 GLITCHLESS CLOCK BUFFER TERABUFFER II DESCRIPTION: FEATURES: • • • • • • • • • • • IDT5T93GL02 The IDT5T93GL02 2.5V differential clock buffer is a user-selectable differential input to two LVDS outputs . The fanout from a differential input to two LVDS

Contextual Info: IDT5T93GL101 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER II INDUSTRIAL TEMPERATURE RANGE 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER II FEATURES: • • • • • • • • • • • IDT5T93GL101 DESCRIPTION: Guaranteed Low Skew < 75ps max

corelis JTAG CONNECTOR

Abstract: PCI-100 asset boundary scan "programmable clock" i2c JTAG CONNECTOR 5T9820NL corelis jtag corelis JTAG CONNECTOR parallel i2c programmable output regulator "Programmable Clock" 6 pin JTAG CONNECTOR
Contextual Info: EVALUATION BOARD FOR IDT5T98xx EVALUATION BOARD FOR IDT5T98xx TABLE OF CONTENTS INTRODUCTION Introduction . 1 Board Overview Block Diagram . 1

diode in40

Abstract: Diode Mark ON B14 Q127 xn13
Contextual Info: 1.8V MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 40 BIT WIDE CONFIGURATION IDT72P51767 IDT72P51777 5,242,880 bits 10,485,760 bits FEATURES • • • • • • • • • • • • Choose from among the following memory density options: IDT72P51767  Total Available Memory = 5,242,880 bits

CK410

Abstract: CK409 CK410B DB1200G DSC67
Contextual Info: IDTCV128 1-TO-12 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE 1-TO-12 DIFFERENTIAL CLOCK BUFFER IDTCV128 DESCRIPTION: FEATURES: The CV128 differential buffer complies with Intel DB1200G rev. 0.5, and is designed to work in conjunction with the main clock of CK409, CK410/CK410M

Contextual Info: 1.8V MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 36 BIT WIDE CONFIGURATION 1,179,648 bits 2,359,296 bits 4,718,592 bits • FEATURES • • • • • • • • • Choose from among the following memory density options: IDT72P51749  Total Available Memory = 1,179,648 bits

Contextual Info: IDT5T93GL061 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II INDUSTRIAL TEMPERATURE RANGE 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II DESCRIPTION: FEATURES: • • • • • • • • • • • IDT5T93GL061 The IDT5T93GL061 2.5V differential clock buffer is a user-selectable

Contextual Info: DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT IDT82V2052E FEATURES: • • • • • Dual channel E1 short haul line interfaces Supports HPS Hitless Protection Switching for 1+1 protection without external relays Single 3.3 V power supply with 5 V tolerance on digital interfaces

Contextual Info: 1.8V MULTI-QUEUE FLOW-CONTROL DEVICES 8 QUEUES 36 BIT WIDE CONFIGURATION 589,824 bits 1,179,648 bits 2,359,296 bits 4,718,592 bits • FEATURES • • • • • • • • • Choose from among the following memory density options: IDT72P51339  Total Available Memory = 589,824 bits

Contextual Info: SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT IDT82V2041E FEATURES • • • • • • Single channel T1/E1/J1 short haul line interfaces Supports HPS Hitless Protection Switching for 1+1 protection without external relays Programmable T1/E1/J1 switchability allowing one bill of material for any line condition

Table-49

Abstract: IDT82V2041E TQFP44
Contextual Info: SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT IDT82V2041E FEATURES • • • • • • Single channel T1/E1/J1 short haul line interfaces Supports HPS Hitless Protection Switching for 1+1 protection without external relays Programmable T1/E1/J1 switchability allowing one bill of material for any line condition

IC-7031

Abstract: 82V2082 IDT82V2052E LP21 TQFP80
Contextual Info: DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT IDT82V2052E FEATURES: • • • • • Dual channel E1 short haul line interfaces Supports HPS Hitless Protection Switching for 1+1 protection without external relays Single 3.3 V power supply with 5 V tolerance on digital interfaces

GR-1244-CORE

Abstract: GR-253-CORE IDT82V3280 GR-1377-CORE 19.440 MHz TCXO
Contextual Info: WAN PLL IDT82V3280 Version 2 June 19, 2006 6024 Silver Creek Valley Road, San Jose, CA 95138 Telephone: 800 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775 Printed in U.S.A. 2006 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry

circuit diagram for automatic voltage regulator G

Abstract: GR-1244-CORE GR-253-CORE IDT82V3255
Contextual Info: WAN PLL IDT82V3255 Version 2 June 19, 2006 6024 Silver Creek Valley Road, San Jose, CA 95138 Telephone: 800 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775 Printed in U.S.A. 2006 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry

XN07

Abstract: Q127 wd2m
Contextual Info: 1.8V MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 40 BIT WIDE CONFIGURATION IDT72P51767 IDT72P51777 5,242,880 bits 10,485,760 bits FEATURES • • • • • • • • • • • • Choose from among the following memory density options: IDT72P51767 ⎯ Total Available Memory = 5,242,880 bits

Contextual Info: IDT5T93GL101 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER II INDUSTRIAL TEMPERATURE RANGE 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER II FEATURES: • • • • • • • • • • • IDT5T93GL101 DESCRIPTION: Guaranteed Low Skew < 75ps max

Contextual Info: IDT5T93GL061 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II INDUSTRIAL TEMPERATURE RANGE 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II DESCRIPTION: FEATURES: • • • • • • • • • • • IDT5T93GL061 The IDT5T93GL061 2.5V differential clock buffer is a user-selectable

Contextual Info: 1.8V MULTI-QUEUE FLOW-CONTROL DEVICES 8 QUEUES 36 BIT WIDE CONFIGURATION 589,824 bits 1,179,648 bits 2,359,296 bits 4,718,592 bits • FEATURES • • • • • • • • • Choose from among the following memory density options: IDT72P51339  Total Available Memory = 589,824 bits

LP21

Abstract: TQFP80 PULS12
Contextual Info: DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT IDT82V2042E FEATURES: • • • • • • Dual channel T1/E1/J1 short haul line interfaces Supports HPS Hitless Protection Switching for 1+1 protection without external relays Programmable T1/E1/J1 switchability allowing one bill of material for any line condition