DS641 Search Results

DS5000

Abstract: DS6417 DS6417P
Contextual Info: DALLAS SEMICONDUCTOR DS6417 CyberCard EV 4M-Bit NV SRAM FEATURES PIN ASSIGNMENT • Greater than 50,000 insertion connector life • Durable and rugged • Ground pin makes first and breaks last • User-insertable memory • Capacities from 256K bits to 4M bits of nonvolatile

Virtex-4QV

Abstract: microblaze interface of jtag to UART in VHDL Virtex4 uart uart vhdl code fpga uart vhdl fpga virtex 6 spartan6 datasheet vhdl spartan 3a vhdl code for uart communication Spartan-6 FPGA
Contextual Info: MicroBlaze Debug Module MDM (v1.00f) DS641 June 24, 2009 Product Specification Introduction LogiCORE Facts This document provides the design specification for the MicroBlaze™ Debug Module (MDM) which enables JTAG-based debugging of one or more MicroBlaze processors.

Contextual Info: DS6417 DALLAS SEMICONDUCTOR DS6417 CyberCard EV 4M-Bit NV SRAM PIN ASSIGNMENT FEATURES • Greater than 50,000 insertion connector life • Durable and rugged • Ground pin makes first and breaks last • User-insertable memory • Capacities from 256K bits to 4M bits of nonvolatile

Contextual Info: CS8421 32-bit, 192-kHz Asynchronous Sample Rate Converter Features  175 dB Dynamic Range  Bypass Mode  –140 dB THD+N  Time Division Multiplexing TDM Mode  No Programming Required  Attenuates Clock Jitter  Multiple Device Outputs are Phase Matched

CS8421

Abstract: CS8421-DZZR varispeed -616PC5/616P5 AN270 AN282 CDB8421
Contextual Info: CS8421 32-bit, 192-kHz Asynchronous Sample Rate Converter Features  175 dB Dynamic Range  Bypass Mode  –140 dB THD+N  Time Division Multiplexing TDM Mode  No Programming Required  Attenuates Clock Jitter  No External Master Clock Required

CDB8421

Abstract: CS8421 CS8421-CNZ CS8421-CNZR CS8421-CZZ CS8421-CZZR CS8421-DZZ CS8421-DZZR
Contextual Info: CS8421 32-bit, 192 kHz Asynchronous Sample Rate Converter z Flexible 3-Wire Serial Digital Audio Input and Features z 175 dB Dynamic Range z –140 dB THD+N z No Programming Required z No External Master Clock Required z Supports Sample Rates up to 211 kHz

DS1868

Abstract: LM 4440 AUDIO AMPLIFIER CIRCUIT DS1230y-200 battery date codes circuit diagram laptop motherboard Scans-049 texas instrument catalog 74ls DS1666-50 st c031 s1040 diode
Contextual Info: S ystem E x t e n s i o n Data Book CPU Supervisors Digital Potentiometers Silicon Timed Circuits Thermal Products DALLAS SEMICONDUCTOR Copyright 1994 Dallas Semiconductor Corporation, Dallas, Texas All Rights Reserved. Circuit diagrams are included to illustrate typical semiconductor applications. Complete information sufficient for

varispeed -616PC5/616P5

Abstract: CS8421 varispeed CDB8421 CS8421-CNZ CS8421-CZZ CS8421-DZZ
Contextual Info: CS8421 32-bit, 192 kHz Asynchronous Sample Rate Converter Features General Description No programming required 175 dB Dynamic Range –140 dB THD+N Flexible 3-wire serial digital audio input port 16, 20, 24, or 32-bit data I/O Supports 128*Fs Master Mode only ,

Contextual Info: ML6415 S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation GENERAL DESCRIPTION FEATURES The ML6415 is a dual Y/C 4th-order Butterworth lowpass video filter optimized for minimum overshoot and flat group delay. The device also contains a summing circuit

varispeed

Abstract: CS84213
Contextual Info: CS8421 32-bit, 192-kHz Asynchronous Sample Rate Converter Features  175 dB Dynamic Range  Bypass Mode  –140 dB THD+N  Time Division Multiplexing TDM Mode  No Programming Required  Attenuates Clock Jitter  No External Master Clock Required

Contextual Info: MaxGard MaxGard Interconnection Systems – Accessories 30-400/600 Amp Plugs, Connectors, Receptacles, Inlets and Interlocked Receptacles Replacement Interiors For Receptacles, Connectors, Plugs & Male Inlets Corresponding Male Interior Assembly Corresponding Female

DS2228

Abstract: DS3700 DS2271 DS1217M DS2244T DS2250 DS2253 DS6417 conformal DS1217
Contextual Info: DALLAS SEMICONDUCTOR 4401 South Beltwood Parkway Dallas, Texas 75244-3292 972 371-4000 Date: January 07, 1999 Subject: PRODUCT CHANGE NOTICE - A90501 Description: Conformal Coat Change Description of Change: Dallas Semiconductor is making a material change in the conformal coat process on all board level

CS8421

Abstract: varispeed -616PC5/616P5 CS8421-DZZR AN270 AN282 CDB8421 varispeed
Contextual Info: CS8421 32-bit, 192 kHz Asynchronous Sample Rate Converter Features  175 dB Dynamic Range  Bypass Mode  –140 dB THD+N  Time Division Multiplexing TDM Mode  No Programming Required  Attenuates Clock Jitter  No External Master Clock Required

AV RF modulator

Abstract: modulator VCR rf channel trap circuit VCR modulator 27mhz transmitter circuit audio video modulator Micro Linear TA 2092 N tv rf modulator video modulator
Contextual Info: ML6415 S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation GENERAL DESCRIPTION FEATURES The ML6415 is a dual Y/C 4th-order Butterworth lowpass video filter optimized for minimum overshoot and flat group delay. The device also contains a summing circuit

cs84210

Abstract: varispeed -616PC5/616P5 CS8421 AN270 CDB8421 CS8421-CNZ CS8421-CNZR CS8421-CZZ CS8421-CZZR CS8421-DZZ
Contextual Info: CS8421 32-bit, 192 kHz Asynchronous Sample Rate Converter Features ! 175 dB Dynamic Range ! Master and Slave Modes for Both Input and Output ! –140 dB THD+N ! Bypass Mode ! No Programming Required ! Time Division Multiplexing TDM Mode ! No External Master Clock Required

aspi-024-aspi-s402

Abstract: ML510 xilinx mig user interface design VIRTEX-5 DDR2 VIRTEX-5 DDR2 controller virtex ml510 xc5vlx130t ChipScope XAPP778 XPS IIC
Contextual Info: ML510 MIG Design Creation Using ISE 11.1, MIG 3.0 and ChipScope™ Pro 11.1 May 2009 Overview ƒ Hardware Setup ƒ Software Requirements ƒ CORE Generator™ software – Memory Interface Generator MIG ƒ Modify Design – Add ChipScope Pro Cores to Design

3.5mm audio jack isolated switch

Abstract: 330uF 35 v capacitor DS6412 EUA6412A 3.5mm stereo headphone jack
Contextual Info: EUA6412A 2.6-W Stereo Audio Power Amplifier with Four Selectable Gain Settings DESCRIPTOIN FEATURES The EUA6412A is a stereo audio power amplifier. When driving 1 W into 8–Ω speakers, the EUA6412A has less than 0.8% THD+N across its specified frequency range. Included

A6412A

Abstract: EUA6412 EUA6412QIR1 EUA6412QIT1 3.5mm stereo headphone jack DS6412
Contextual Info: EUA6412 2.6-W Stereo Audio Power Amplifier with Four Selectable Gain Settings DESCRIPTOIN FEATURES The EUA6412 is a stereo audio power amplifier. When driving 1 W into 8–Ω speakers, the EUA6412 has less than 0.8% THD+N across its specified frequency range. Included

Contextual Info: D S 1258K-001 PRELIMINARY H A I I A O DS1258K-001 CyberCard Portable Data Carrier Evaluation Kit s e m ic o n d u c t o r FEATURES PIN ASSIGNMENT • Read or write any Cyber Portable Data Carriers with a PC host • No slot required; connects to parallel printer port

s9081

Abstract: DS9080A S908
Contextual Info: DS908XX DALLAS DS908XX CyberKey/Card Receptacles s e m ic o n d u c to r FEATURES receptacle is specified for a 50,000 insertion/withdrawal-cycle life. • Solid base metal contacts The A or V designation in the part number specifies • Durable and rugged

CS84214

Contextual Info: CS8421 32-bit, 192 kHz Asynchronous Sample Rate Converter Features ! 175 dB Dynamic Range ! Bypass Mode ! –140 dB THD+N ! Time Division Multiplexing TDM Mode ! No Programming Required ! Attenuates Clock Jitter ! No External Master Clock Required ! Multiple Part Outputs are Phase-Matched

AN270

Abstract: AN282 CDB8421 CS8421
Contextual Info: CS8421 32-bit, 192-kHz Asynchronous Sample Rate Converter Features  175 dB Dynamic Range  Bypass Mode  –140 dB THD+N  Time Division Multiplexing TDM Mode  No Programming Required  Attenuates Clock Jitter  No External Master Clock Required

CS8412 DAC

Abstract: CS8421 CS8421-DZZR varispeed -616PC5/616P5 AN270 AN282 CDB8421 CS8412 F136
Contextual Info: CS8421 32-bit, 192 kHz Asynchronous Sample Rate Converter Features ! 175 dB Dynamic Range ! Bypass Mode ! –140 dB THD+N ! Time Division Multiplexing TDM Mode ! No Programming Required ! Attenuates Clock Jitter ! No External Master Clock Required ! Multiple Part Outputs are Phase-Matched

ML505

Abstract: ml507 MT4HTF3264HY-53e VIRTEX-5 DDR2 ps2 controller ML506 aspi-024-aspi-s402 MT4HTF3264HY DS695 VIRTEX-5 DDR2 controller
Contextual Info: ML505/506/507 MIG Design Creation Using ISE 11.1, MIG 3.0 and ChipScope™ Pro 11.1 May 2009 Overview ƒ Hardware Setup ƒ Software Requirements ƒ CORE Generator™ software – Memory Interface Generator MIG ƒ Modify Design – Add ChipScope Pro Cores to Design