DS217 Search Results

DS2175

Abstract: DS2175N DS2175S DS2180A DS2181A HC595
Contextual Info: DS 2175 DALLAS SEMICONDUCTOR FEATURES DS2175 T1/CEPT Elastic Store PIN ASSIGNMENT • Rate buffer for T1 and C E PT transm ission system s • Synchronizes lo o p -tim e d and system tim ed data stream s on fram e boundaries • Ideal forT1 1.544 MHz to CEPT (2.048 MHz), CEPT

Contextual Info: DALLAS SEMICONDUCTOR DS2176 T1 Receive Buffer FEATURES PIN ASSIGNMENT • Synchronizes loop-timed and system-timed T1 data streams s ìg h C 1 24 H VDD RMSYNC C 2 • Two-frame buffer depth; slips occur on frame bound­ aries • Output indicates when slip occurs

DS2175

Abstract: DS2175N DS2175S DS2180A DS2181A HC595
Contextual Info: DS2175 T1/CEPT Elastic Store www.dalsemi.com FEATURES • • • • • • • • PIN ASSIGNMENT Rate buffer for T1 and CEPT transmission systems Synchronizes loop–timed and system timed data streams on frame boundaries Ideal for T1 1.544 MHz to CEPT (2.048

DS2172

Abstract: burst generator ds2172 application note psr1
Contextual Info: DS2172 Application Note Bit Error Rate Tester, V.54 Modem Test Patterns June 6, 1996 The DS2172 can be used to generate and detect the PREPARATORY, ACKNOWLEDGE, and TERMINATION patterns for V.54 modem testing. Figure 1 shows the pattern generator depicted in V.54. The pattern generator in the DS2172 is

ds2172 application note

Abstract: receiver transistor DS2172 32 Bit Counter counter pcr sin01v12 Receiver
Contextual Info: DS2172 Application Note Bit Error Rate Tester, Simplified Receiver Operation April 28, 1997 DS2172 SIMPLIFIED RECEIVER OPERATION DURING REPETITIVE PATTERN MODE PATTERN RECEIVE REGISTERS RL PCR.3 1 RDATA S1 2 SHIFT REGISTER TAP CONTROLLED BY PATTERN LENGTH REGISTER

DS2172

Contextual Info: DS2172 Application Note Bit Error Rate Tester, Repetitive Pattern Operation May, 9 1996 The DS2172 can be used to generate repetitive patterns up to 32 bits in length. Operation of the synchronizer differs in this mode from the Pseudo random Pattern mode. In the Repetitive Pattern mode the receiver looks for a repeating

PS700

Contextual Info: PS700 PS700 Rev. B4 Silicon Errata The PS700 Rev. B4 parts you have received conform functionally to the Device Data Sheet DS21760F , except for the anomalies described below. Microchip does not intend to address the issues listed here in future revisions of the PS700 silicon. It is recommended that you replace the PS700 in existing

BEC26

Abstract: BEC10 th02 DS2172 PS24 PS25 PS26 PS27 PS28 PS29
Contextual Info: DS2172 DALLAS s e m ic o n d u c t o r FEATURES DS2172 Bit Error R a te T e s te r B E R T PIN ASSIGNMENT 1G enerates/D etects digital bit patterns for analyzing, evaluating and troubleshooting digital com m unica­ tions system s 1 — < O Q O W O O O Q

BEC23

Abstract: DS2172 PS22 PS29 PS30 INTEL PR8
Contextual Info: DS2172 DS2172 Bit Error Rate Tester BERT FEATURES PIN ASSIGNMENT TDATA TDIS TCLK VSS VDD RCLK RDIS RDATA • Generates/Detects digital bit patterns for analyzing, evaluating and troubleshooting digital communications systems • Operates at speeds from DC to 52 MHz

C32-C40

Abstract: 50-Pin DIP Connector SMD diode DS1 DS2174 SMD TQFP microcontroller DS87C520-ECL how to use in crystal osc 11.0592mhz ECU-V1H102KBM DS2174DK SEMICONDUCTOR dallas
Contextual Info: DS2174DK Enhanced Bit Error-Rate Tester Design Kit www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS2174DK is a fully integrated demonstration kit for the DS2174 enhanced bit error-rate tester BERT . This demo kit contains all the necessary circuitry to evaluate the device in all modes of

Contextual Info: DS2175 T1/CEPT Elastic Store www.dalsemi.com FEATURES • • • • • • • • PIN ASSIGNMENT Rate buffer for T1 and CEPT transmission systems Synchronizes loop–timed and system timed data streams on frame boundaries Ideal for T1 1.544 MHz to CEPT (2.048

si24

Contextual Info: DS2176 F U LL DATA S H E E T A V A IL A B L E - C A L L 214-450-3836 DALLAS DS2176 T 1 R eceive Buffer s e m ic o n d u c to r PIN ASSIGNMENT FEATURES • Synchronizes loop-timed and system-timed T 1 data streams C C C C 3 22 4 21 AC 5 20 C CC DC SCH CLK C

TFDU circuit

Abstract: marking code C9 TFDU 4100 circuit MCP2140 MMUN2111LT1
Contextual Info: MCP2140 MCP2140 Rev. A Silicon/Data Sheet Errata The MCP2140 Rev. A parts you have received conform functionally to the MCP2140 device data sheets DS21790A , with the exception of the anomaly described below. These issues has been addressed in the MCP2140

32-PIN

Abstract: DS2172 DS2172T DS2172TN PS22 PS30 O.151
Contextual Info: DS2172 Bit Error Rate Tester BERT www.dalsemi.com FEATURES PIN ASSIGNMENT TDATA TDIS TCLK VSS VDD RCLK RDIS RDATA Generates/Detects digital bit patterns for analyzing, evaluating and troubleshooting digital communications systems Operates at speeds from DC to 52 MHz

DS2174

Abstract: DS2174Q DS2174QN
Contextual Info: DS2174 EBERT www.maxim-ic.com § § § § § § § § § ORDERING INFORMATION DS2174Q DS2174QN 44-Pin PLCC 0°C to +70°C 44-Pin PLCC -40°C to +85°C RDAT2 RDAT1 RDAT0 RCLK_EN RCLK VDD D7 D6 D5 D4 D3 6 5 4 3 2 1 44 43 42 41 40 § PIN ASSIGNMENT Generates and detects digital patterns for

DS2180A

Abstract: DS2175 DS2181A DS2186 DS2187 DS2280 DS2281 DS2281-075 DS2281-120 2BL4
Contextual Info: DS2280/DS2281 DS2280/DS2281 DALLAS SEMICONDUCTOR T 1 Line Card Stik C E P T Line Card Stik FEATURES PIN ASSIGNMENT • Pretested, snap-in T1 or CEPT line card DS2280 DS2281-075 DS2281-120 o T1 Line Card 75 ohm CEPT Line Card 120 ohm CEPT Line Card DS2175 ID

DS2172

Abstract: AN458
Contextual Info: COMMUNICATIONS CIRCUITS Application Note 458: May 08, 2001 App Note 332: DS2172 Simplified Receiver Operation DS2172 Bit Error Rate Tester BERT simplified receiver operation during repetitive pattern mode. Operation During Repetitive Pattern Mode PATTERN RECEIVE REGISTERS

DS2186

Abstract: DS2187 DS2176 DS2176N DS2176Q DS2180A 193s
Contextual Info: DS2176 DS2176 T1 Receive Buffer PIN ASSIGNMENT • Synchronizes loop–timed and system–timed T1 data 1 24 VDD 2 23 SCLKSEL RCLK 3 22 SYSCLK RSER 4 21 SSER A 5 20 SLIP B 6 19 SBIT8 C 7 18 SMSYNC D 8 17 SIGFRZ SCHCLK 9 16 SFSYNC SM0 10 15 ALN SM1 11 14 FMS

32-PIN

Abstract: DS2172 PS22 PS29 PS30
Contextual Info: DS2172 Bit Error Rate Tester BERT www.dalsemi.com Generates/Detects digital bit patterns for analyzing, evaluating and troubleshooting digital communications systems Operates at speeds from DC to 52 MHz Programmable polynomial length and feedback taps for generation of any other

DS2172

Abstract: DS2172T DS2172TN PS22 PS29 PS30 ps12 type BEC23
Contextual Info: DS2172 Bit Error Rate Tester BERT www.dalsemi.com PIN ASSIGNMENT TDATA TDIS TCLK VSS VDD RCLK RDIS RDATA Generates/Detects digital bit patterns for analyzing, evaluating and troubleshooting digital communications systems Operates at speeds from DC to 52 MHz

DS2175

Contextual Info: RELIABILITY MONITOR PRODUCT MONITOR DATE DATE CODE ASSEMBLY FACILITY ASSEMBLY LOT NO PROCESS TYPE PACKAGE TYPE DS2175 Jul-97 9712 D1 ANAM, K. DN702069AAJ 2.0µ OXIDE 16 SOIC STRESS/JOB NO. READPOINT Sample Size/No. of Fails Preconditioning (P/C): T/C: -55°C to +125°C, 10~

Contextual Info: n A I I A S s e m ic o n d u c to r FEATURES DS2172 Bit Error Rate Tester BERT PIN ASSIGNMENT • G enerates/Detects digital bit patterns for analyzing, evaluating and troubleshooting digital com m unica­ tions systems • O perates at speeds from DC to 52 MHz

Contextual Info: DALLAS SEMICONDUCTOR DS2175 T1/CEPT Elastic Store FEATURES PIN ASSIGNMENT • Rate buffer for T 1 and CEPT transm ission system s • Synchronizes loop-tim ed and system tim ed data stream s on fram e boundaries • Ideal for T1 1.544 MHz to CEPT (2.048 MHz), CEPT

Contextual Info: DS2176 DALLAS SEMICONDUCTOR DS2176 T 1 Receive Buffer FEATURES PIN ASSIGNMENT • Synchronizes loop-timed and system-timed T1 data streams 1 24 □ VDD RMSYNC C 2 s ig h C 23 □ SCLKSEL r c lk C 22 □ SYSCLK • Two-frame buffer depth; slips occur on frame bound­