DS100517 Search Results

74LS

Abstract: DS1005 DS1005-100 DS1005-125 DS1005-60 DS1005-75 DS1005M DS1005S
Contextual Info: DS 1005 DALLAS r DS1005 5-Tap Silicon Delay Line s e m ic o n d u c to r FEATURES PIN ASSIGNMENT • All-silicon time delay IN 1 14 ] Vcc IN £ 1 16 H VCC NC 2 13 ] NC NC C 2 15 n NC C 3 14 H NC NC 3 12 TAP 2 C 4 13 H TAP 1 • Stable and precise over temperature and voltage

Contextual Info: DALLAS SEMICONDUCTOR DS1005 5-Tap Silicon Delay Line PIN ASSIGNMENT FEATURES • All-silicon time delay IN • 5 taps equally spaced NC • Delay tolerance ±2 ns or ±3%, whichever is greater NC • Stable and precise over temperature and voltage range TAP 2

FPD1500SOT89

Abstract: FPD2250SOT89 FPD2250SOT89CE MIL-HDBK-263 FPD2250SOT FPD2250
Contextual Info: FPD2250SOT89CE FPD2250SOT8 9CELow-Noise High-Linearity Packaged pHEMT LOW-NOISE HIGH-LINEARITY PACKAGED pHEMT NOT FOR NEW DESIGNS Package: SOT89 Features      Optimum Technology Matching Applied   GaAs HBT GaAs MESFET InGaP HBT 60% Power-Added Efficiency

RF3171TR13

Abstract: GMSK wireless data transmission RF3171 DCS1800 DCS1900 EGSM900 GSM900 PCS1900 polar architecture 8PSK BLOCK DIAGRAM
Contextual Info: RF3171 QUAD-BAND GMSK POLAR EDGE TXM, 2 UMTS SWITCH PORTS GND GND GND GND GND GND HB RFIN 1 GND Package Style: Module, 7.00mmx6.00mmx1.00mm 30 29 28 27 26 25 24 GND 2           20 W3 Bias and Power Control VBATT 5 VCTL4 6 Switch

Contextual Info: DS1005 DALLAS DS1005 5-Tap Silicon Delay Line s e m ic o n d u c t o r FEATURES PIN DESCRIPTION • All-silicon time delay • 5 taps equally spaced itC 1 14 ] V c c nc£ 2 13 3 12 ]]TAP 1 TAP 4 Ü Delay tolerance +/- 2 ns or +/- 2%, whichever ncQ is greater

74LS

Abstract: DS1005 DS1005-100 DS1005-125 DS1005-150 DS1005-75 DS1005M DS1005S delay line 400ns
Contextual Info: DALLAS SEMICO ND UCTOR CORP OTE D | 2bl4130 □□□2074 b | T-47-13 ^ Dallas Semiconductor 5 TAP SILICON DELAY LINE 31 FEATURES DS1005 14-Pin DIP DS1005M 8-Pin DIP DS1005S 16-Pin SOIC PIN CONNECTIONS • All silicon time delay . • 5 TAPS equally spaced. Delay

74LS

Abstract: DS1005 DS1005-60 DS1005G DS1005H DS1005K DS1005M DS1005S
Contextual Info: DS1005 DALLAS SEMICONDUCTOR DS1005 5-Tap Silicon Delay Line PIN ASSIGNMENT FEATURES • All-silicon time delay IN • 5 taps equally spaced • Delay tolerance ±2 ns or ±3%, whichever is greater • Stable and precise over temperature and voltage range • Leading and trailing edge accuracy

DS1005-60

Abstract: 74LS DS1005 DS1005-100 DS1005-125 DS1005-150 DS1005-175 DS1005-75 DS1005M DS1005S
Contextual Info: DS1005 5-Tap Silicon Delay Line www.dalsemi.com FEATURES All-silicon time delay 5 taps equally spaced Delay tolerance ±2 ns or ±3%, whichever is greater Stable and precise over temperature and voltage range Leading and trailing edge accuracy Economical Auto-insertable, low profile

Contextual Info: Preliminary Technical Information XPTTM 650V IGBTs GenX4TM IXXK160N65B4 IXXX160N65B4 VCES IC110 VCE sat tfi(typ) Extreme Light Punch Through IGBT for 10-30kHz Switching = = ≤ = 650V 160A 1.80V 90ns TO-264 (IXXK) Symbol Test Conditions VCES VCGR TJ = 25°C to 175°C

3g hsdpa signal Schematic Diagram

Abstract: LQG15HN12NJ02D RF3165 RF3165PCBA-410
Contextual Info: RF3165 RF31653V 1750MHz WCDMA Linear Power Amplifier Module 3V 1750MHZ W-CDMA LINEAR POWER AMPLIFIER MODULE NOT FOR NEW DESIGNS 28dBm Linear Output Power  42% Peak Linear Efficiency  28dB Linear Gain  -41dBc ACLR @ ±5MHz  HSDPA Capable IM NC 10 VCC2

6V-0-6V

Abstract: precision waveform generator hy 214 74LS DS1005 DS1005-100 DS1005-125 DS1005-60 DS1005-75 DS1005M
Contextual Info: DS1005 DS1005 5-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay • 5 taps equally spaced IN 1 14 Vcc IN 1 16 VCC NC 2 13 NC NC 2 15 NC • Delay tolerance ±2 ns or ±3%, whichever is greater NC 3 12 TAP 1 TAP 2 4 11 NC NC 5 10 TAP 3

Contextual Info: DS1005 DALLAS SEMICONDUCTOR DS1005 5-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay C1 c2 NC [ 3 TAP 2 c4 NC [ 5 TAP 4 [ 6 GND [ 7 IN • 5 taps equally spaced NC • Delay tolerance ±2 ns or ±3%, whichever is greater • Stable and precise over temperature and voltage

Contextual Info: DS1005 DALLAS SEMICONDUCTOR DS1005 5-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay IN [ • 5 taps equally spaced NC [ C 1 14 3 Vcc IN C 1 2 13 ] NC NC £ 2 3 12 ] TAP1 4 11 10 ] TAPS NC C 3 • Delay tolerance ± 2 ns or ±3%, whichever is greater

FPD1500SOT89

Abstract: FPD2250SOT89 FPD2250SOT89E TRANSISTOR SSG 111 oint 4410 HBT transistor s parameters measures
Contextual Info: FPD2250SOT89 FPD2250SOT8 9 Low-Noise High-Linearity Packaged pHEMT LOW-NOISE HIGH-LINEARITY PACKAGED pHEMT NOT FOR NEW DESIGNS Package: SOT89 Features      Optimum Technology Matching Applied   GaAs HBT GaAs MESFET InGaP HBT 60% Power-Added Efficiency

Contextual Info: D S 1005 DALLAS SEMICONDUCTOR FEATURES DS1005 5-Tap Silicon Delay Line PIN ASSIGNMENT • All-silicon time delay • 5 taps equally spaced Vcc IN □ 1 16 □ Vcc NC NC □ 2 15 □ NC 3 14 4 13 □ TAP 1 5 12 6 7 11 □ TAP 3 10 □ NC 8 9 □ TAP 5 E TAP 2 E

Contextual Info: DS1005 5-Tap Silicon Delay Line www.dalsemi.com FEATURES All-silicon time delay 5 taps equally spaced Delay tolerance ±2 ns or ±3%, whichever is greater Stable and precise over temperature and voltage range Leading and trailing edge accuracy Economical Auto-insertable, low profile

Contextual Info: DS1005 DALLAS SEMICONDUCTOR DS1005 5-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay IN • 5 taps equally spaced [_ 1 NC [ • Delay tolerance ±2 ns or ±3%, whichever is greater • Stable and precise over temperature and voltage

74LS

Abstract: DS1005 DS1005-100 DS1005-125 DS1005-60 DS1005-75 DS1005M DS1005S
Contextual Info: DS1005 DS1005 5-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay • 5 taps equally spaced IN 1 14 Vcc IN 1 16 VCC NC 2 13 NC NC 2 15 NC • Delay tolerance ±2 ns or ±3%, whichever is greater NC 3 12 TAP 1 TAP 2 4 11 NC NC 5 10 TAP 3

Contextual Info: DALLAS SEMICONDUCTOR DS1005 5-Tap Silicon Delay Line PIN ASSIGNM ENT FEATURES • All-silicon time delay IN • 5 taps equally spaced NC • Delay tolerance ±2 ns or +3%, whichever is greater NC TAP 2 • Stable and precise over tem perature and voltage range