DS1004 Search Results

DS1425L-F5

Abstract: rtc ds1307 dallas ds2501 dallas ds2501 Datasheet dallas ds1280 DS2501 ds1642-150 DS1669 replacement ds2501 Datasheet DS1608S
Contextual Info: ORDERING INFORMATION DEVICE DS0621–SDK DS0630 DS1000 DS1000–IND DS1003 DS1004 DS1005 DS1007 DS1010 DS1012 DS1013 DS1020 DS1021 DS1033 DS1035 DS1040 PACKAGE TYPE Software Software 14–Pin DIP 8–Pin DIP 16–Pin SOIC 8–Pin SOIC 8–Pin DIP 8–Pin SOIC

pt45

Contextual Info: LatticeSC Family Data Sheet DS1004 Version 01.2, June 2006 LatticeSC Family Data Sheet Introduction June 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks

Contextual Info: LatticeSC/M Family Data Sheet DS1004 Version 02.1, June 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 139 to 942 I/Os • 700MHz global clock; 1GHz edge clocks

Contextual Info: LatticeSC Family Data Sheet DS1004 Version 01.4b, February 2007 LatticeSC Family Data Sheet Introduction November 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os

Contextual Info: LatticeSC/M Family Data Sheet DS1004 Version 01.6, August 2007 LatticeSC/M Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os

2-bit comparator

Abstract: LFSC3GA15E-5F900I PR77A PR55D pr94a diode transistor pt36c pt36C PB110C pb127d PB138
Contextual Info: LatticeSC/M Family Data Sheet DS1004 Version 01.8, November 2007 LatticeSC/M Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os

Contextual Info: DS1004 5-Tap High Speed Silicon Delay Line www.dalsemi.com FEATURES PIN ASSIGNMENT All-silicon timing circuit Five delayed clock phases per input Precise tap-to-tap nominal delay tolerances of ±0.75 and ±1 ns Input-to-tap 1 delay of 5 ns Nominal Delay tolerances of ±1.5 ns

Contextual Info: LatticeSC Family Data Sheet DS1004 Version 01.5, March 2007 LatticeSC Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks

Ablebond 71

Abstract: 9727
Contextual Info: 08/08/2002 RELIABILITY REPORT FOR DS1004, Rev E1 Dallas Semiconductor 4401 South Beltwood Parkway Dallas, TX 75244-3292 Prepared by: Ken Wendel Reliability Engineering Manager Dallas Semiconductor 4401 South Beltwood Pkwy. Dallas, TX 75244-3292 Email : ken.wendel@dalsemi.com

PB68C

Abstract: LFSCM3GA40EP1
Contextual Info: LatticeSC Family Data Sheet DS1004 Version 01.4a, January 2007 LatticeSC Family Data Sheet Introduction November 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os

DS1004

Abstract: DS1004M DS1004M-2 DS1004M-3 DS1004M-4 DS1004M-5 DS1004Z DS1004Z-2 DS1004Z-3 DS1004Z-4
Contextual Info: Ì DS1004 5-Tap High Speed Silicon Delay Line WÈ w mmmommtm www.dalsemi.com PIN ASSIGNMENT FEATURES All-silicon timing circuit Five equally delayed clock phases per input Precise tap-to-tap delay tolerances of ±0.5, ±0.75, or ±1 ns Input-to-tap 1 delay of 5 ns

Contextual Info: D S1004 n A I I A C DS1004 5-Tap High-Speed Silicon Delay Line s e m ic o n d u c to r PIN ASSIGNMENT FEATURES • All-silicon timing circuit • Five equally delayed clock phases per input • Precise tap-to-tap delay tolerances of ±0.5, +0.75, or ±1 ns

DS1004

Abstract: DS1004M DS1004M-2 DS1004M-3 DS1004M-4 DS1004M-5 DS1004Z DS1004Z-2 DS1004Z-3 DS1004Z-4
Contextual Info: DS 1004 DALLAS SEMICONDUCTOR DS1004 5-Tap High-Speed Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon timing circuit IN C • Five equally delayed clock phases per input • Precise ta p -to -tap delay tolerances of ±0.5, ±0.75, or ±1 ns Z l Vcc

Contextual Info: D S 1004 DALLAS SEMICONDUCTOR DS1004 5-Tap High-Speed Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon timing circuit • Five equally delayed clock phases per input • Precise tap-to-tap delay tolerances of ±0.5, ±0.75, or ±1 ns IN L 1 8 □

DS1004Z-004

Contextual Info: DS1004 DALLAS SEMICONDUCTOR DS1004 5-Tap High-Speed Silicon Delay Line PIN ASSIGNMENT FEATURES • All-silicon timing circuit • Five equally delayed clock phases per input • Precise tap-to-tap delay tolerances of ±0.5, ±0.75, or ±1 ns IN C 1 TAP 2 [ I

pb127d

Contextual Info: LatticeSC/M Family Data Sheet DS1004 Version 02.2, December 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 139 to 942 I/Os • 700MHz global clock; 1GHz edge clocks

Contextual Info: LatticeSC/M Family Data Sheet DS1004 Version 01.9, January 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os

DS1669-100

Abstract: TQFP 100 pin Socket 4 pin dip switch DS2401 PACKAGE 16 pin DIP socket DS1804 NV 2 pin dip switch ds1232(ind) data sheet ds1642-150 DS1620S
Contextual Info: ORDERING INFORMATION DEVICE DS0621–SDK DS1000 DS1000–IND DS1003 DS1004 DS1005 DS1007 DS1010 DS1012 DS1013 DS1020 DS1021 DS1033 DS1035 DS1040 PACKAGE TYPE Software 14–Pin DIP 8–Pin DIP 16–Pin SOIC 8–Pin SOIC 8–Pin DIP 8–Pin SOIC 14–Pin DIP

Contextual Info: LatticeSC/M Family Data Sheet DS1004 Version 02.0, March 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 139 to 942 I/Os

Contextual Info: DS1004 5-Tap High Speed Silicon Delay Line www.dalsemi.com PIN ASSIGNMENT FEATURES All-silicon timing circuit Five delayed clock phases per input Precise tap-to-tap nominal delay tolerances of ±0.75 and ±1 ns Input-to-tap 1 delay of 5 ns Nominal Delay tolerances of ±1.5 ns

PB110C

Abstract: PB124A pt36C SCM15 BA5 904 AF P PL80B PR55D pr94a diode transistor pt36c transistor pt42c
Contextual Info: LatticeSC/M Family Data Sheet DS1004 Version 02.3, January 2010 LatticeSC/M Family Data Sheet Introduction January 2010 Data Sheet DS1004 Features – 1 to 7.8 Mbits memory – True Dual Port/Pseudo Dual Port/Single Port – Dedicated FIFO logic for all block RAM

PB97A

Abstract: PR45C pr77a
Contextual Info: LatticeSC/M Family Data Sheet DS1004 Version 02.4, December 2011 LatticeSC/M Family Data Sheet Introduction January 2010 Data Sheet DS1004 Features  High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 139 to 942 I/Os • 700MHz global clock; 1GHz edge clocks

DS1004

Abstract: DS1004M DS1004M-2 DS1004M-3 DS1004M-4 DS1004M-5 DS1004Z DS1004Z-2 DS1004Z-3 DS1004Z-4
Contextual Info: DS1004 5-Tap High Speed Silicon Delay Line www.dalsemi.com FEATURES PIN ASSIGNMENT All-silicon timing circuit Five delayed clock phases per input Precise tap-to-tap nominal delay tolerances of ±0.75 and ±1 ns Input-to-tap 1 delay of 5 ns Nominal Delay tolerances of ±1.5 ns

PB80D

Abstract: PR87A PR98A PR96A PB110C pr94a diode pt36C pr77a transistor pt36c transistor pt42c
Contextual Info: LatticeSC/M Family Data Sheet DS1004 Version 02.3, January 2010 LatticeSC/M Family Data Sheet Introduction January 2010 Data Sheet DS1004 Features – 1 to 7.8 Mbits memory – True Dual Port/Pseudo Dual Port/Single Port – Dedicated FIFO logic for all block RAM