DS0011 Search Results

Z8E001

Abstract: Z8E000
Contextual Info: Product Update UP003802-0703 Errata to Z8E000/Z8E001 Silicon Introduction This Product Update lists precautions regarding the TOUT and TXVAL functions of the Z8E000 and Z8E001 microcontrollers. Related Documentation Z8E000 Product Specification DS0036 Z8E001 Product Specification (DS0011)

Contextual Info: DATA SHEET DS0011 September 2011 PanelX 38mm Trackball DESCRIPTION Designed for demanding industrial environments, PanelX builds on the proven design of Pretorian Technology’s PanelPro™ panel mounting trackballs. They incorporate a PanelPro 38mm trackball into a convenient brushed stainless steel

Z8E00110PEC

Abstract: 10D-13 zilog z8p Z8E00110SSC Z8E001 Z8E00110HEC Z8E00110HSC Z8E00110PSC Z8E00110SEC otp z8e001
Contextual Info: DATA SHEET Z8E001 1 FEATURE-RICH Z8PLUS ONE-TIME PROGRAMMABLE OTP MICROCONTROLLER FEATURES Part Number ROM (KB) RAM* (Bytes) Speed (MHz) 64 10 Z8E001 1 Note: * General-Purpose Microcontroller Core Features ¥ All Instructions Execute in one 1 µs Instruction Cycle

MPPC 001

Abstract: MPPC 001 ci mppc CADDR15 9711S 9711PT4
Contextual Info: 9711 Data Compression Processor Hi/fnTM supplies two of the Internet’s most important raw materials: compression and encryption. Hi/fn is also the world’s first company to put both on a single chip, creating a processor that performs compression and encryption at

XTR2N0800

Contextual Info: XTRM Series XTR2N0800 IE W HIGH-TEMPERATURE, 80V N-CHANNEL POWER MOSFET FAMILY DESCRIPTION ▲ Minimum BVDSS = 100V. ▲ Allowed VGS range –5.5V to +5.5V. ▲ Operational beyond the -60°C to +230°C temperature range. ▲ Low RDS on o XTR2N0825: 1.8 Ω @ 230°C

xc2s300e pinouts

Abstract: LP1-D12 L43P xc2s300e l36n xc2s50e L26N L28N XC2S200E L18P
Contextual Info: Spartan-IIE 1.8V FPGA Family: Pinout Tables R DS077-4 v1.0 November 15, 2001 Preliminary Product Specification Pin Definitions Dedicated Pin Direction Description GCK0, GCK1, GCK2, GCK3 No Input Clock input pins that connect to Global Clock buffers. These pins

DS001-3

Abstract: SPARTAN XC2S50 sr 100/25 PCI33 XC2S100 XC2S15 XC2S150 XC2S200 XC2S30 XC2S50
Contextual Info: Spartan-II 2.5V FPGA Family: DC and Switching Characteristics R DS001-3 v2.4 August 28, 2001 Preliminary Product Specification Definition of Terms In this document, some specifications may be designated as Advance or Preliminary. These terms are defined as follows:

SPARTAN-II xc2s200 pq208 block diagram

Abstract: fpga frame buffer vhdl examples
Contextual Info: Spartan-II 2.5V FPGA Family: Functional Description R DS001-2 v2.0 September 18, 2000 Preliminary Product Specification Architectural Description Spartan-II Array The Spartan-II user-programmable gate array, shown in Figure 1, is composed of five major configurable elements:

qhw050a1-q

Abstract: lucent DC-DC POWER MODULE
Contextual Info: Data Sheet September 11, 2000 QHW050A1-Q, QHW075A1-Q, and QHW100A1-Q Power Modules: dc-dc Converters; 36 to 75 Vdc Input, 5 Vdc Output; 50 W to 100 W Features The QHW Series Power Modules use advanced, surfacemount technology and deliver high-quality, efficient, and compact dc-dc conversion.

XC2S30 PIN OUT

Abstract: xc2s50
Contextual Info: Spartan-II 2.5V FPGA Family: DC and Switching Characteristics R DS001-3 v2.2 January 19, 2001 Preliminary Product Specification Definition of Terms In this document, some specifications may be designated as Advance or Preliminary. These terms are defined as follows:

p181 g8

Abstract: 105 p180 g8 707 p181 g5209 p115 SPARTAN XC2S50 SPARTAN-II xc2s200 pq208 tms 374 transistor be p88 P140
Contextual Info: Spartan-II 2.5V FPGA Family: Pinout Tables R DS001-4 v2.4 April 30, 2001 Preliminary Product Specification Pin Definitions Pin Name Dedicated Pin Direction Description GCK0, GCK1, GCK2, GCK3 No Input Clock input pins that connect to Global Clock Buffers. These pins become

circuit diagram of digital set top box

Abstract: MT20* MICROTUNE MT2084 microtune MT2082 digital tuner MT2081 MT208
Contextual Info: Product Brief MT2084 World-Standard Digital Cable Tuner The MicroTuner MT2084 is an advanced, low-power companion tuner to the MT2082, enabling low cost multi-tuner STBs. Product Overview Related Product Information: • Press Release • Related Products

MT2082

Abstract: MT2084 2 way rf splitter circuit diagram 2 way RF splitter, circuit diagram Tuner demodulator datasheet MT2081 "3 way splitter", circuit diagram mICROTUNE
Contextual Info: Product Brief MT2082 World-Standard Digital Cable Tuner The MicroTuner MT2082 is an advanced single-chip broadband tuner with integrated splitter and loop-through. Product Overview Related Product Information: • Press Release • Related Products  Order Information

SPARTAN XC2S50

Abstract: SPARTAN-II xc2s200 pq208 xc2s50-tq144 XC2S50 SPARTAN-II xc2s50 pq208 XC2S100 xc2s200 pq208 SPARTAN-II xc2s100 pq208 VQ100 XC2S150
Contextual Info: Spartan-II 2.5V FPGA Family: Introduction and Ordering Information R DS001-1 v2.0 September 18, 2000 Preliminary Product Specification Introduction The Spartan -II 2.5V Field-Programmable Gate Array family gives users high performance, abundant logic resources,

Contextual Info: Data Sh ee t D O _ i Z8E001 • F e a t u r e - R ic h Z 8 p l u s O n e - T im e P r o g r a m ­ m a b l e ( O T P M ic r o c o n t r o l l e r M a k e s S m a l l P r o d u c t io n R u n s E c o n o m ic a l l y F e a s ib l e N Totally Logical FEATURES

vhdl code for pcm bit stream generator

Contextual Info: Preliminary Data Sheet January 2002 ORCA ORT4622 Field-Programmable System Chip FPSC Four-Channel x 622 Mbits/s Backplane Transceiver Introduction Lattice has developed a solution for designers who need the many advantages of FPGA-based design implementation, coupled with high-speed serial backplane data transfer. The 622 Mbits/s backplane transceiver offers a clockless, high-speed interface for

DISPERSION COMPENSATING FIBER

Abstract: DCF fiber dcf fiber parameters AP99-020 1725-type GR-1312-CORE 1725 edfa DS99-353
Contextual Info: Preliminary Data Sheet February 2003 TriQuint Optoelectronics 1725-Type Gain Block Erbium-Doped Fiber Amplifier Features • intCTOR QICuONDU i r TSEM Characterized by extremely flat gain over a wide 1.5 µm wavelength range, the 1725-Type Gain Block EDFA features a

Contextual Info: Spartan-II 2.5V FPGA Family: Introduction and Ordering Information R DS001-1 v2.3 November 1, 2001 Introduction Preliminary Product Specification • The Spartan -II 2.5V Field-Programmable Gate Array family gives users high performance, abundant logic resources,

diode k5 10-16

Abstract: SPARTAN-II xc2s200 pq208 block diagram
Contextual Info: Spartan-II 2.5V FPGA Family: Introduction and Ordering Information R DS001-1 v2.2 March 5, 2001 Introduction Preliminary Product Specification • The Spartan -II 2.5V Field-Programmable Gate Array family gives users high performance, abundant logic resources,

B1133

Contextual Info: Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information R DS077-1 v1.1 June 27, 2002 Introduction Preliminary Product Specification • The Spartan -IIE 1.8V Field-Programmable Gate Array family gives users high performance, abundant logic

Hytrel G

Abstract: schematic power diode laser module pump DS92-212LWP agere photodiode 263JLG DS98-339LWP
Contextual Info: Data Sheet March 2000 263-Type 0.98 µm Pump Laser with Fiber Grating Applications • Erbium-doped fiber amplifier systems: — Optical preamplifiers — In-line optical repeaters — Power-booster amplifiers Description Offering superior wavelength stability, the 263-Type Laser

XC2S15-VQ100

Abstract: g5209 SPARTAN-II xc2s200 pq208 SPARTAN-II xc2s200 pq208 pin assignments XC2S150 IR P116 microcontroller based automatic power factor correction MULTIPLEXER IC max 455 SPARTAN XC2S50 PQ208
Contextual Info: Spartan-II 2.5V Family Field Programmable Gate Arrays R DS001 v1.0 March 14, 2000 - Advance Product Specification Introduction • The Spartan -II family is the second generation high-volume production FPGA solution, based on the highly successful Virtex™ family architecture. The family delivers all

SPARTAN-II xc2s200 pq208

Abstract: DS-00121 Spartan-II pin details DS001-2 upd 2816 CS144 FG256 PQ208 17S00A VQ100
Contextual Info: Spartan-II 2.5V FPGA Family: Functional Description R DS001-2 v2.1 March 5, 2001 Preliminary Product Specification Architectural Description Spartan-II Array The Spartan-II user-programmable gate array, shown in Figure 1, is composed of five major configurable elements:

circuit diagram for portable dvd china

Abstract: ITU-J83 AU8820 DVB-C Demodulator microtune GB20600-2006 PB-00174 digital cable tv channel receiver
Contextual Info: Product Brief AU8824 Integrated Single-Chip CTTB DTMB and DVB-C HDTV Demodulator The AU8824 is a highly integrated, fully GB20600-2006 and ITU-T J.83 Annex A/C compliant, high-performance CTTB (DTMB) and DVB-C demodulator supporting all digital terrestrial TV and cable broadcast