DRIVING POINT AND TRANSFER Search Results

cdv304

Abstract: capacitive coupling ethernet CDC111 CDCV304 CDCVF111 HPA8133A TLK3104SA
Contextual Info: Application Report SCAA049 – November 2001 Using TI’s CDC111/CDCVF111 With TLK3104SA Serial Transceiver for Gigabit Ethernet and Backplane Applications Kal Mustafa High Performance Analog/CDC ABSTRACT This application report discusses jitter transfer of TI’s CDC111/CDCVF111 clock drivers

QS34X245Q3

Abstract: QS74FCT534 driving point and transfer AN-41
Contextual Info: AN-41 Q Using Quality Semiconductor’s QuickSwitch Technology on the PCI Local Bus QUALITY SEMICONDUCTOR, INC. Application Note AN-41 Abstract The Peripheral Component Interconnect PCI Local Bus is designed to increase the data transfer rate between a processor and its peripheral components,

DM 024

Abstract: DDR400 PC3200 DDR266 DDR333 512mb sodimm pc2700 200 pin samsung
Contextual Info: White Electronic Designs W3EG264M72EFSUxxxD4 ADVANCED* 1GB – 2x64Mx72 DDR SDRAM, UNBUFFERED, FBGA FEATURES DESCRIPTION Fast data transfer rate: PC-2100, PC-2700 and PC3200 The W3EG264M72EFSU is a 2x64Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR

max1461

Abstract: max14611 MAX14611ETD MAX3378
Contextual Info: 19-6276; Rev 0; 4/12 EVALUATION KIT AVAILABLE MAX14611 Quad Bidirectional Low-Voltage Logic-Level Translator General Description The MAX14611 is a quad bidirectional logic-level translator that provides the level shifting necessary to allow data transfer in a multivoltage system. Externally applied voltages, VCC and VL, set the logic levels on either side of

Contextual Info: HD61202- Dot Matrix Liquid Crystal Graphic Display Column Driver Description Features HD61202 is a column (segment) driver for dot matrix liquid crystal graphic display systems. It stores the display data transferred from a 8-bit micro controller in the internal display RAM and

omron E5C

Abstract: E5EN-Q3HMT-500 simple fire alarm circuit diagram PLC based fire alarm system block diagram OMRON E5CN RELAY OMRON E5EN E5EN-C3ML-500 omron pid pressure omron pid example signal conditioning circuit for pt100 4-20 mA
Contextual Info: Digital Temperature Controllers E5EN This Best-selling General-purpose Temperature Controller Is Now Even Better. Setup Tool Cable and Support Software Are Also Available. • Controllers now available with analog inputs. • Faster sampling at 250 ms. • Transfer output provided for easy output to recorders.

Contextual Info: H D66107T- LCD Driver for High Voltage D escription • • The HD66107T is a m ulti-output, high du ty ratio LCD driver used for large capacity dot m atrix LCD panels. It consists of 160 LCD drive circuits w ith a display d u ty ratio u p to

Contextual Info: N E W E5_C-T Programmable Temperature Controller Digital Controller Easy-to-read, simple and dependable Program control » Set Up to 8 Progra m s wit h 32 Seg men ts Each . » H i g h - c o n t ra s t display » Easy set-up and operation with a Special Sof tware

HYB25D256400AT-7.5

Abstract: HYB25D256800T-7 DDR200 DDR266A DDR266B HYB25D256400T-7 HYB25D256400T-8 HYB25D256800T-8 TSOP66
Contextual Info: HYB25D256400/800T/AT 256-MBit Double Data Rata SDRAM Features CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency MHz DDR266A DDR266B DDR200 -7 -7.5 -8 133 125 100 143 133 125 . • Double data rate architecture: two data transfers per clock cycle

DDR200

Abstract: DDR266A HYB25D256400AT-7 HYB25D256400AT-8 HYB25D256800AT-7 HYB25D256800AT-8 TSOP66
Contextual Info: HYB25D256400/800AT 256-MBit Double Data Rata SDRAM Features CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency MHz DDR266A DDR200 -7 -8 133 100 143 125 • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted

c0301

Abstract: ADN2811 ADN2811ACP-CML ADN2811ACP-CML-RL CP-48 GR-253-CORE STM-16 Fiber Optic regenerator 28
Contextual Info: a OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp ADN2811 FEATURES Meets SONET Requirements for Jitter Transfer/ Generation/Tolerance Quantizer Sensitivity: 4 mV Typ Adjustable Slice Level: ؎100 mV 1.9 GHz Minimum Bandwidth Patented Clock Recovery Architecture

AN-514

Abstract: DM74AS373 DM74AS374
Contextual Info: ABSTRACT This paper presents detailed examples of bus timing calculations for both synchronous and asynchronous busses, showing that bus throughput can be maximized by taking into account the characteristics and limitations of the transceiver technology being used. Based on these examples, a performance analysis of the currently available high speed bus interface technologies is made in terms of their maximum attainable transfer rate on both types of backplane busses.

schematic diagram PWM solar charger - 10A

Abstract: mppt Charge Controller design and circuit mppt charge controller schematic mppt solar charger schematic 12V Solar Charge Controller mppt ic microcontroller based solar charger Solar mppt schematic mppt solar charger schematic schematic diagram MPPT 12v Solar Charge Controller PWM series type
Contextual Info: AN2946 Application note Solar-LED streetlight controller with 25 W LED lamp driver and 85 W battery charger based on the STM32F101Rx Introduction The solar-LED streetlight controller described in this application note is designed to achieve an 85 W solar energy battery charger and a 25 W LED lamp driver. During the daytime the

shorted stub logic

Abstract: sdya016 472 pf
Contextual Info: Basic Design Considerations for Backplanes SZZA016 June 1999 1 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest

TTL to LVTTL level shifter

Contextual Info: a Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp ADN2819 FEATURES Meets SONET Requirements for Jitter Transfer/ Generation/Tolerance Quantizer Sensitivity: 4 mV Typ Adjustable Slice Level: ؎ 100 mV 1.9 GHz Minimum Bandwidth

LTC5567

Contextual Info: LTC6417 1.6GHz Low Noise High Linearity Differential Buffer/16-Bit ADC Driver with Fast Clamp DESCRIPTION FEATURES 1.6GHz –3dB Small Signal Bandwidth Low Distortion Driving 50Ω Load, 2.4VP-P Out –100dBc/–69dBc HD2/HD3 at 140MHz –80dBc IM3 and 46dBm OIP3 at 140MHz

h10s raltron

Abstract: ADN2819 ADN2819ACP-CML ADN2819ACP-CML-RL CP-48 GR-253-CORE OC-24 H10S-19
Contextual Info: a Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp ADN2819 FEATURES Meets SONET Requirements for Jitter Transfer/ Generation/Tolerance Quantizer Sensitivity: 4 mV Typ Adjustable Slice Level: ؎100 mV 1.9 GHz Minimum Bandwidth Patented Clock Recovery Architecture

ISSI 346

Abstract: DDR333 DDR400 IS43R16320A ISSI 605 ISSI 742
Contextual Info: ISSI IS43R16320A 32Meg x 16 512-MBIT DDR SDRAM NOVEMBER 2006 FEATURES DEVICE OVERVIEW • • ISSI’s 512-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 536,870,912-bit memory

CDC111

Abstract: CDCV304 CDCVF111 SLK2501 capacitive coupling ethernet
Contextual Info: Application Report SCAA050 – November 2001 Using TI’s CDCVF111 With SLK2501 Serial Gigabit Transceiver for SONET and Gigabit Ethernet Applications Kal Mustafa High Performance Analog/CDC ABSTRACT SONET/SDH and gigabit ethernet applications all have stringent timing requirements,

Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UPSR100 Preliminary CMOS IC HIGH PRECISION CC/CV PRIMARY SIDE REGULATOR „ DESCRIPTION The UTC UPSR100 is a primary control unit for switch mode charger and adapter applications. The controlled variable is transferred by an auxiliary winding from the secondary to the

Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UPSR100 Preliminary CMOS IC HIGH PRECISION CC/CV PRIMARY SIDE SWITCHING REGULATOR  DESCRIPTION The UTC UPSR100 is a primary control unit for switch mode charger and adapter applications. The controlled variable is transferred by an auxiliary winding from the secondary to the

Contextual Info: DMA Transfer Controller DISTINCTIVE CHARACTERISTICS • • Channel interleave operations Masked data pattern matching for search operations V ectored interrupts on selected transfer conditions Base registers for repetitive operations Tw o independent m ulti-function channels

HD44100H

Contextual Info: H D 6 6 1 0 0 F- LCD Driver w ith 80-Channel Outputs The HD66100 description segment driver with 80 LCD drive circuits is the improved version of the no longer current HD44100H LCD driver with 40 circuits. It is composed of a shift register, an 80-bit

microdisplay

Abstract: The MicroDisplay MAX4220 MAX4544 MD640G3 MD800G4 MD640 FPC CONNECTOR 20pin The MicroDisplay Corporation LED Display Theory
Contextual Info: MD800G4 Grayscale 800 x 600 MicroMonitor General Description The MD800G4 device is an active matrix liquid crystal display with 800 × 600 spatial resolution. Integrated horizontal and vertical shift registers reduce driving logic. The device is easy to interface, with a single monochrome or four