DOUBLE DATA RATE Search Results

lm815

Contextual Info: TOSHIBA TENTATIVE TC59LM815/07/03BFT-22,-24,-30 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 4,194,304-WORDSX4BANKSX 16-BITS DOUBLE DATA RATE FAST CYCLE RAM 8,388,608-WORDSX4BANKSX8-BITS DOUBLE DATA RATE FAST CYCLE RAM 16,777,216-WORDSX4BANKSX4-BITS DOUBLE DATA RATE FAST CYCLE RAM

Contextual Info: T O SH IB A TC59LM814/06/02BFT-22,-24,-30 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 4,194,304-WORDSX4BANKSX16-BITS DOUBLE DATA RATE FAST CYCLE RAM 8,388,608-WORDSX4BANKSX8-BITS DOUBLE DATA RATE FAST CYCLE RAM 16,777,216-WORDSX4BANKSX4-BITS DOUBLE DATA RATE FAST CYCLE RAM

lm814

Abstract: cyble thelia TC59 A14A9
Contextual Info: TOSHIBA TC59LM814/06BFT-22,-24,-30 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 4,194,304-WORDSX4BANKSX16-BITS DOUBLE DATA RATE FAST CYCLE RAM 8,388,608-WORDSX4BANKSX8-BITS DOUBLE DATA RATE FAST CYCLE RAM DESCRIPTION TC59LM814/06BFT are a CMOS Double Data Rate Fast Cycle Random Access Memory DDR

lm814

Abstract: ID32-001
Contextual Info: TOSHIBA TC59LM814/06BFT-22,-24,-30 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 4,194,304-WORDSX4BANKSX16-BITS DOUBLE DATA RATE FAST CYCLE RAM 8,388,608-WORDSX4BANKSX8-BITS DOUBLE DATA RATE FAST CYCLE RAM DESCRIPTION TC59LM814/06BFT are a CMOS Double Data Rate Fast Cycle Random Access Memory DDR

Contextual Info: ispLever CORE TM Double Data Rate DDR SDRAM Controller (Pipelined Version) User’s Guide June 2004 ipug12_03 Double Data Rate (DDR) SDRAM Controller (Pipelined Version) User’s Guide Lattice Semiconductor Introduction DDR (Double Data Rate) SDRAM was introduced as a replacement for SDRAM memory running at bus speeds

lm814

Abstract: C1948
Contextual Info: TOSHIBA TENTATIVE TC59LM814/06BFT-22,-24,-30 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 4,194,304-WORDSX4BANKSX 16-BITS DOUBLE DATA RATE FAST CYCLE RAM 8,388,608-WORDSX4BANKSX8-BITS DOUBLE DATA RATE FAST CYCLE RAM DESCRIPTION TC59LM814/06BFT are a CMOS Double Data Rate Fast Cycle Random Access Memory DDR

HYB18TC512

Abstract: HYB18TC512160BF HYB18TC512160BF-3 HYB18TC512160
Contextual Info: September 2006 HYB18TC512160BF HYB18TC512800BF 512-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.11 Internet Data Sheet HYB18TC512[16/80]0BF 512-Mbit Double-Data-Rate-Two SDRAM HYB18TC512160BF, HYB18TC512800BF

Contextual Info: T O S H IB A TC59LM814/06CFT-50,-55,-60 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 4,194,304-WORDSX4BANKSX 16-BITS DOUBLE DATA RATE FAST CYCLE RAM 8,388,608-WORDSX4BANKSX8-BITS DOUBLE DATA RATE FAST CYCLE RAM DESCRIPTION TC59LM814/06CFT are a CMOS Double Data Rate Fast Cycle Random Access Memory DDR

HYB18T512160BF

Abstract: hyb18t512800bf3s HYB18T512160BF-3.7 HYB18T512800BF-2.5 400B DDR400 HYB18T512400BF HYB18T512800BF HYB18T512400BF-5 HYB18T512400BF-3S
Contextual Info: January 2007 HYB18T512400BF HYB18T512800BF HYB18T512160BF 512-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products Internet Data Sheet R ev . 1 . 05 Internet Data Sheet HYB18T512xxxBF–[2.5…5] 512-Mbit Double-Data-Rate-Two SDRAM HYB18T512400BF, HYB18T512800BF

46LR16200C

Abstract: Mobile DDR SDRAM 43LR16200C
Contextual Info: IS43LR16200C 1M x 16Bits x 2Banks Mobile DDR SDRAM Description The IS43LR16200C is 33,554,432 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 2 banks of 1,048,576 words x 16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2N

HYB18TC256160BF

Contextual Info: February 2007 HYB18T C25616 0 BF 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.21 Internet Data Sheet HYB18TC256160BF 256-Mbit Double-Data-Rate-Two SDRAM HYB18TC256160BF Revision History: 2007-02, Rev. 1.21

DDR2-667C

Contextual Info: December 2006 HYB18T256400BF L HYB18T256800BF(L) HYB18T256160BF(L) 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.0 Internet Data Sheet HYB18T256xx0BF(L)–[25F/…/5] 256-Mbit Double-Data-Rate-Two SDRAM

400B

Abstract: HYB18TC256160AF
Contextual Info: February 2007 HYB18T C25616 0 AF 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.1 Internet Data Sheet HYB18TC256160AF 256-Mbit Double-Data-Rate-Two SDRAM HYB18TC256160AF Revision History: 2007-02, Rev. 1.1

HYB18TC256160AF

Abstract: 400B
Contextual Info: April 2007 HYB18T C25616 0 AF 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.20 Internet Data Sheet HYB18TC256160AF 256-Mbit Double-Data-Rate-Two SDRAM HYB18TC256160AF Revision History: 2007-04, Rev. 1.20

NtRAM

Abstract: BGA package tray 64
Contextual Info: High Speed SRAM Code Information 1/4 Last Updated : November 2008 K7XXXXXXXX - XXXXXXX 1 2 3 4 5 6 1. Memory (K) 2. Sync SRAM : 7 3. Small Classification A : Sync Pipelined Burst B : Sync Burst D : Double Data Rate I : Double Data Rate II, Common I/O J : Double Data Rate II, Seperate I/O

IRC5

Contextual Info: TC59LM913/05AMG-50,-55,-60 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 8,388,608-WORDS x 4 BANKS × 16-BITS DOUBLE DATA RATE FAST CYCLE RAM 16,777,216-WORDS × 4 BANKS × 8-BITS DOUBLE DATA RATE FAST CYCLE RAM DESCRIPTION TC59LM913/05AMG is a CMOS Double Data Rate Fast Cycle Random Access Memory DDR-FCRAMTM

Contextual Info: TC59LM814/06/02 BFT-22,-24,-30 TOSHIBA TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 4,1 9 4,3 0 4 -W O R D SX 4 BA N K SX 1 6-BITS DOUBLE DATA RATE FAST CYCLE R AM 8,388,608-WORDSX4BANKSX8-BITS DOUBLE DATA RATE FAST CYCLE RAM 16,777,216-WORDSX4BANKSX4-BITS DOUBLE DATA RATE FAST CYCLE RAM

Contextual Info: TC59LM814/06CFT-50,-55,-60 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 4,194,304-WORDS x 4 BANKS × 16-BITS DOUBLE DATA RATE FAST CYCLE RAM 8,388,608-WORDS × 4 BANKS × 8-BITS DOUBLE DATA RATE FAST CYCLE RAM DESCRIPTION TC59LM814/06CFT are a CMOS Double Data Rate Fast Cycle Random Access Memory DDR FCRAMTM

Contextual Info: TC59LM913/05AMG-50,-55,-60 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 8,388,608-WORDS x 4 BANKS × 16-BITS DOUBLE DATA RATE FAST CYCLE RAM 16,777,216-WORDS × 4 BANKS × 8-BITS DOUBLE DATA RATE FAST CYCLE RAM DESCRIPTION TC59LM913/05AMG is a CMOS Double Data Rate Fast Cycle Random Access Memory DDR -FCRAMTM

46LR16200C

Abstract: Mobile DDR SDRAM
Contextual Info: IS43/46LR16200C 1M x 16Bits x 2Banks Mobile DDR SDRAM Description The IS43/46LR16200C is 33,554,432 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 2 banks of 1,048,576 words x 16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2N

Contextual Info: IS43LR16200C Advanced Information 1M x 16Bits x 2Banks Mobile DDR SDRAM Description The IS43LR16200C is 33,554,432 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 2 banks of 1,048,576 words x 16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2N

Contextual Info: I S43LR32100C Advanced Information 512K x 32Bits x 2Banks Mobile DDR SDRAM Description The IS43LR32100C is 33,554,432 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 2 banks of 524,288 words x 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2N

HYB18TC512160BF-3S

Abstract: HYB18TC512
Contextual Info: September 2007 HYB18T C51280 0 BF HYB18T C51216 0 BF 512-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.21 Internet Data Sheet HYB18TC512[80/16]0BF 512-Mbit Double-Data-Rate-Two SDRAM HYB18TC512800BF, HYB18TC512160BF

Contextual Info: ESMT Preliminary M13S2561616A (2S) DDR SDRAM 4M x 16 Bit x 4 Banks Double Data Rate SDRAM Features  Double-data-rate architecture, two data transfers per clock cycle  Bi-directional data strobe (DQS)  Differential clock inputs (CLK and CLK ) 