DM74LS4 Search Results

26series

Abstract: hex to 7 segment decoder line driver 74ABT240 74AC240 74AC540 74ACQ240 74ACT1284 DM74145 DM74LS47
Contextual Info: Logic Products by Function Line Driver Products Logic Product Family Product Description Package Voltage Node MM88C29 74C CMOS Quad Single-Ended Line Driver DIP 5 other MM88C30 74C CMOS Dual Differential Line Driver DIP SOIC 5 other DM74LS47 Bipolar-LS BCD to 7-Segment Decoder/Driver

Contextual Info: R C H U - P S E M IC O N D U C T O R tm DM74LS47 BCD to 7-Segment Decoder/Driver with Open-Collector Outputs General Description Features The ’LS47 accepts fo u r lines of BC D 8421 input data, gen­ erates th e ir com plem ents internally and decodes the data

Contextual Info: May 1992 DM54LS447/DM74LS447 BCD to 7-Segment Decoder/Driver with Open-Collector Outputs General Description The ’LS447 is the same as the ’LS247 except that the Out­ put OFF Voltage, Vqh is specified as 7.0 V rather than 15V, with the same Ioh limit of 250

Contextual Info: & June 1989 54LS42/DM54LS42/DM74LS42 BCD/Decimal Decoders General Description Features These BCD-to-decimal decoders consist of eight inverters and ten, four-input NAND gates. The inverters are connect­ ed in pairs to make BCD input data available for decoding

DM74LS453N

Abstract: 8336 74LS153 C1995 DM54LS453 DM54LS453J DM74LS453 DM74LS453J J24F N24C
Contextual Info: DM54LS453 DM74LS453 Quad 4 1 Multiplexer General Description Features Benefits The quad 4 1 Mux selects one of four inputs C0 through C3 specified by two binary select inputs A and B The true data is output on Y Propagation delays are the same for inputs and addresses and are specified for 50 pF loading Outputs

J24F

Abstract: LS469 N24C DM54LS469J DM74LS469 DM74LS469J DM74LS469N *LS469
Contextual Info: DM74LS469 8-Bit Up/Down Counter General Description The ’LS469 is an 8-bit synchronous up/down counter with parallel load and hold capability. Three function-select inputs LD, UD, CBI provide one of four operations which occur synchronously on the rising edge of the clock (CK).

ls469

Abstract: DM54LS469 DM54LS469J DM74LS469 DM74LS469J DM74LS469N J24F N24C C1995 L8333
Contextual Info: DM54LS469 DM74LS469 8-Bit Up Down Counter General Description The ‘LS469 is an 8-bit synchronous up down counter with parallel load and hold capability Three function-select inputs LD UD CBI provide one of four operations which occur synchronously on the rising edge of the clock (CK)

DM54LS469AJ

Abstract: DM74LS469A DM74LS469AJ DM74LS469AN DM74LS469AV J24F N24C V28A LS469A
Contextual Info: DM74LS469A 8-Bit Up/Down Counter General Description The ’LS469A is an 8-bit synchronous up/down counter with parallel load and hold capability. Three function-select inputs LD, UD, CBI provide one of four operations which occur synchronously on the rising edge of the clock (CK).

161mux

Abstract: LEI-4 74150 PIN DIAGRAM
Contextual Info: DM54LS450/DM74LS450 16:1 Multiplexer General Description Features/Benefits The 16:1 Mux selects one of sixteen inputs, EO through E15, specified by four binary select inputs, A, B, C, and D. The true data is output on Y and the inverted data on W. Propa­

LS460

Contextual Info: LS460 National Semiconductor DM54LS460/DM74LS460 10-Bit Comparator General Description Features/Benefits The 'LS460 is a 10-bit comparator with true and comple­ ment comparison status outputs. The device compares two 10-bit data strings A g -A o and Bg - B 0 to establish if this

Contextual Info: LS42 National Semiconductor 54LS42/DM54LS42/DM74LS42 BCD/Decimal Decoders General Description Features These BCD-to-decimal decoders consist of eight inverters and ten, four-input NAND gates. The inverters are connect­ ed in pairs to make BCD input data available for decoding

IC 74LS153 pin diagram

Abstract: IC 74LS153 pin diagram of ic 74ls153
Contextual Info: LS453 National Semiconductor DM54LS453/DM74LS453 Quad 4:1 Multiplexer General Description Features/Benefits The quad 4:1 Mux selects one of four inputs, CO through C3, specified by two binary select inputs, A and B. The true data is output on Y. Propagation delays are the same for inputs

Contextual Info: LS460 JlA National Semiconductor DM54LS460/DM74LS460 10-Bit Comparator General Description Features/Benefits The 'LS460 is a 10-bit comparator with true and comple­ ment comparison status outputs. The device compares two 10-bit data strings Ag-Ao and Bg-B o to establish if this

Contextual Info: February 1992 Semiconductor & DM74LS490 Dual Decade Counter General Description Features The ’LS490 contains a pair of high speed 4-stage ripple counters. Each half of the ’LS490 has individual Clock, Mas­ ter Reset and Master Set Preset 9 inputs. Each section

LS48

Abstract: DM74LS46 7segment
Contextual Info: National Semiconductor 54LS48/DM74LS48 BCD to 7-Segment Decoder General Description The 'LS48 translates four lines of BCD 8421 input data into the 7-segment numeral code and provides seven corre­ sponding outputs having pull-up resistors, as opposed to

Contextual Info: July 1989 Semiconductor & DM54LS491A/DM74LS491A 10-Bit Counter General Description Features The ten-bit counter can count up, count down, set, and load 2 LSB’s, 2 MSB’s and 6 middle bits high or low as a group. All operations are synchronous with the clock. SET over­

Contextual Info: , , July 1989 Semiconductor DM54LS460A/DM74LS460A 10-Bit Comparator General Description Features The ’LS460A is a 10-bit comparator with true complement comparison status outputs. The device compares two 10-bit data strings A g-A O and B g-B O to establish if this data is

101712

Contextual Info: February 1992 Semiconductor DM74LS40 Dual 4-Input NAND Buffer General Description This device contains two independent gates each of which perform the logic NAND function. Connection Diagrams Dual-In-Line Package TL/F/10171 -1 Order Number DM74LS40M or DM74LS40N

Contextual Info: July 1989 Semiconductor & DM54LS461A/DM74LS461A Octal Counter General Description The LS461A is an 8-bit synchronous co un ter w ith parallel load, clea r and hold capability. T w o fun ctio n se le ct inputs 10, 11 provide one o f fo u r ope ra tio ns w hich occur synchro­

Contextual Info: EM ICONDUCTQ R t DM74LS469 8-Bit Up/Down Counter General Description The ’ LS469 is an 8-bit synchronous up/down counter with parallel load a nd hold capability. Three fu n ctio n-se lect inputs LD, UD, CBI provide one of fo u r operations w hich occur

54LS40DMQB

Abstract: DM74LS40N 54LS40FMQB 54LS40LMQB DM74LS40M E20A J14A M14A N14A
Contextual Info: NATIONAL SEMICOND i L O G I O 31E D • laSQUES GGbTTflS 3 T'IJ-iS-00 CTH National éüekSemiconductor 54LS40/DM74LS40 Dual 4-Input NAND Buffer General Description This device contains two independent gates each of which perform the logic NAND function. Connection Diagrams

blanking bcd to seven segment circuit diagram

Abstract: DM74LS47 code bcd to 7 segment display for TOTEM POLE DM74LS47 DM74LS47N DM74LS47M M16A MS-001 N16E 7-Segment Display Driver with Decoder
Contextual Info: Revised March 2000 DM74LS47 BCD to 7-Segment Decoder/Driver with Open-Collector Outputs General Description Features The DM74LS47 accepts four lines of BCD 8421 input data, generates their complements internally and decodes the data with seven AND/OR gates having open-collector

DM54LS498J

Abstract: DM74LS498J DM74LS498N J24F N24C LS498
Contextual Info: LS498 a National Semiconductor DM54LS498/DM74LS498 Octal Shift Register General Description The LS498 is an 8 -bit synchronous shift register with parallel load and hold capability. Two function select inputs lo, l-t provide one of four operations which occur synchronously

C1995

Abstract: DM54LS498 DM54LS498J DM74LS498 DM74LS498J DM74LS498N J24F N24C
Contextual Info: DM54LS498 DM74LS498 Octal Shift Register General Description The LS498 is an 8-bit synchronous shift register with parallel load and hold capability Two function select inputs I0 I1 provide one of four operations which occur synchronously on the rising edge of the clock (CK)