DIOD M7 Search Results

SD840

Contextual Info: UNITRODE CORP DD1107S 3 f 92D 9 3 4 7 9 6 3 UNITRODE CORP 11075 POWER SCHOTTKY RECTIFIERS D U SD820 U SD 835 U SD 840 U SD 845 24A Pk, up to 45V DESC R IPT IO N The U S D 8 0 0 series of Schottky barrier power rectifiers is ideally suited for output rectifiers and catch diod e s In

Contextual Info: M ITSUBISHI HIGH S P E E D CM O S M74HC11P M74HC11DP T R IP L E 3 -IN P U T P O S IT IV E AND GATE DESCRIPTION The M74HC11 is a sem iconductor inte grated c ircu it con­ PIN CONFIGURATION TOP VIEW sisting of th re e 3-in put po s itiv e -lo g ic AND, usable as ne ga­

Contextual Info: MITSUBISHI HIGH SPEED CMOS M74HC10P M74HC10DP T R IP L E 3 -IN P U T P O S IT IV E NAND GATE DESCRIPTION The M 74H C 10 is a sem iconductor integrated c ircu it con­ sisting of three 3-in put p o s itiv e -lo g ic NAND, PIN CONFIGURATION TOP VIEW usable as

Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M74HC266P/FP/DP QUADRUPLE 2 -IN P U T E X C L U S IV E NOR GATE DESCRIPTION T h e M 7 4 H C 2 6 6 is a s e m ic o n d u c to r in te g r a te d c irc u it c o n ­ PIN CONFIGURATION TOP VIEW s is tin g of fo u r 2 -in p u t e x c lu s iv e N O R g a te s .

Contextual Info: MI TSUBI SHI HIGH S P E E D CMOS M74HC109P DUAL J-K F L I P - F L O P WI TH S E T AND R E S E T DESCRIPTION The M 74H C 109 is a sem iconductor integrated c irc u it con­ PIN CONFIGURATION TOP VIEW sisting of tw o po s itiv e -e d g e trig g e re d J -K flip -flo p s w ith in­

Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M74HC393P DUAL 4-S TA G E BINARY R IP P L E COUNTER DESCRIPTION T h e M 7 4 H C 3 9 3 is a sem iconductor in teg ra te d circuit con­ sisting of tw o asynchronous 4 -b it PIN CONFIGURATION TOP VIEW binary (h e x a d e c ilm a l)

Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M74HC534P OCTAL 3-S TA TE IN V E R TIN G D -T Y P E F L IP -F L O P DESCRIPTION The M 74H C 534 is a sem ico ndu ctor inte grated c irc u it con­ PIN CONFIGURATION TOP VIEW sisting of eig h t positive e d g e trig g e re d D -type flip -flo p s

Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M74HC4024P/FP/DP 7-STAGE BINARY R IP P L E COUNTER DESCRIPTION T h e M 7 4 H C 4 0 2 4 is a sem iconductor in teg rated circuit con­ sisting of an asynchronous 7 -s ta g e PIN CONFIGURATION TOP VIEW binary counter with

Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M74HC151P 8 -IN P U T DATA S E L E C T O R /M U L T IP L E X E R DESCRIPTION T h e M 7 4H C 151 is a sem ico nd u cto r integrated circu it co n ­ PIN CONFIGURATION TOP VIEW sisting of an 8 -lin e to 1 -line data selecto r/m u ltip lexer.

Contextual Info: ps M IT S U B IS H I HIGH SPEED CMOS M74HC2S7P V ' vs * S-i»'' V P - * QUADRUPLE 2 -IN P U T DATA S E L E C T O R /M U L T IP L E X E R W IT H 3-S TA TE O U T P U T S DESCRIPTION T h e M 7 4 H C 2 5 7 is a sem iconductor in teg rated circuit con­ PIN CONFIGURATION (TOP VIEW

Contextual Info: MITSUBISHI HIGH SPEED CMOS M74HC161P M74HC161DP P R E S E T T A B L E 4 -B IT BINARY COUNTER W IT H ASYNCHRONOUS R E S E T DESCRIPTION T h e M 7 4 H C 1 6 1 is a s e m ic o n d u c to r in te g ra te d c irc u it c o n ­ s is tin g of a p re s e tta b le

M74HC153P

Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M74HC153P/FP/DP DUAL 4 -IN P U T DATA S E L E C T O R /M U L T IP L E X E R DESCRIPTION T h e M 7 4 H C 1 5 3 is a sem iconductor in teg rated circuit con­ PIN CONFIGURATION TOP VIEW sisting of tw o 4 -lin e to 1 -lin e data s electo rs/m ultiplexers.

M74HC541P

Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M74HC541P/FP/DWP OCTAL 3-S TA T E N O N IN VERTIN G B U F F E R /L IN E D R IV E R /L IN E R E C EIVER DESCRIPTION T h e M 7 4 H C 5 4 1 is a sem iconductor in teg rated circuit con­ PIN CONFIGURATION TOP VIEW sisting of 3 -s ta te non-inverting buffers each with eight in d e ­

Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M74HC157P/FP/DP QUADRUPLE 2 -IN P U T NONINVERTING DATA S E L E C T O R /M U L T IP L E X E R DESCRIPTION T h e M 7 4 H C 1 5 7 is a sem ico nductor in teg rated circuit con­ PIN CONFIGURATION TOP VIEW sisting of four 2 -lin e to 1-lin e data s electo rs/m ultiplexers.

Contextual Info: M IT S U B IS H I <DIGITAL ASSP> M74HC374-1P/FP OCTAL 3-S TA T E N O N IN VE R TIN G D -T Y P E F L IP -F L O P DESCRIPTION T h e M 7 4 H C 3 7 4 -1 is an in teg ra te d circuit chip consisting of eigh t p o s itiv e -e d g e -trig g e re d 3 -s ta te PIN CONFIGURATION TOP VIEW

M74HC540P

Abstract: 74HC540FP
Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M74HC540P/FP/DWP OCTAL 3-S TA T E IN V E R TIN G B U F F E R /L IN E D R IV E R /L IN E R E C EIVER DESCRIPTION T h e M 7 4 H C 5 4 0 is a sem ico nductor in teg rated circuit con­ PIN CONFIGURATION TOP VIEW sisting of 3 -s ta te inverting buffers each with eight in d e p e n ­

Contextual Info: MITSUBISHI HIGH SPEED CMOS M 74HC04P M 74HC04DP HEX IN VE R TE R DESCRIPTION The M 74H C 04 is a sem iconductor integ rate d c irc u it con­ PIN CONFIGURATION TOP VIEW sisting of six inverters. FEATURES • H ig h -sp e e d : 10ns typ. (C L= 1 5 p F , V CC= 5 V )

ci la 7610

Abstract: tpl 624
Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M74HC251P/FP/DP 8 -IN P U T DATA S E L E C T O R /M U L T IP L E X E R W IT H 3 -S T A T E O U TPU TS DESCRIPTION T h e M 7 4 H C 2 5 1 is a sem iconductor in teg rated circuit con­ PIN CONFIGURATION TOP VIEW sisting of an 8 -lin e to 1 -lin e data s e le c to r/m u ltip le x e r with

Contextual Info: M ITSU B ISH I HIGH SPEED CMOS M74HC112P/FP/DP DUAL i-K F L IP -F L O P W ITH S E T AND R ESET DESCRIPTION T h e M 7 4 H C 1 1 2 is a s e m ic o n d u c to r in te g ra te d c irc u it c o n ­ PIN CONFIGURATION TOP VIEW s is tin g of tw o n e g a t iv e - e d g e tr ig g e r e d J - K flip flo p s w ith in ­

Contextual Info: E S S 6/CANADA/OPTOELEK m 3030bl0 0000334 5 47 E t ICANA F Series FFD-040;FFD-100;FFD-200 rv/ J3 Features • • • • Low Operating Voltage High Responsivity Ultra-Fast Rise and FallTim e Isolated Photodiode Chip • • • Large Active Area W ide Spectral Range

Contextual Info: M ITSU B ISH I HIGH SPEED CMOS M 74H C 139P /FP /D P DUAL 1 -0 F -4 D E C O D E R /D E M U L T IP L E X E R DESCRIPTION The M 74H C 139 is a sem iconductor integrated c ircu it con­ PIN CONFIGURATION TOP VIEW sisting of a 2-b it binary to d iv id e -b y -4 d e c o d e r/d e m u ltip le x ­

M74HC02

Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M74HC02P M74HC02DP QUADRUPLE 2 -IN P U T P O S IT IV E NOR GATE DESCRIPTION The M 74H C 02 is a sem iconductor integrated c ircu it con­ PIN CONFIGURATION TOP VIEW sisting of four 2-in put p o sitive -lo g ic NOR, usable as nega­

pin configuration 74LS10

Abstract: M74HC10P 4000B 74LS10 M74HC10 M74HC10DP of IC 74ls10 CMOS 74LS10 logic diagram of IC 74ls10 74LS10 mitsubishi
Contextual Info: M IT S U B IS H I HIGH S P E E D C M O S M74HC10P M74HC10DP T R IP L E 3 -IN P U T P O S IT IV E NAND G A TE DESCRIPTION The M 74H C 10 is a sem iconductor integrated circu it con­ sisting of three 3-input p o sitive-lo gic PIN CONFIGURATION TOP VIEW NAND, usable as

Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M74HC280P 9 -B IT O D D /EV EN P A R IT Y GENERATOR/CHECKER DESCRIPTION T h e M 7 4 H C 2 8 0 is a sem iconductor in teg rated circuit con­ PIN CONFIGURATION TOP VIEW sisting of a 9 -b it parity g e n e ra to r/c h e c k e r.