M74HC11 Search Results

74LS11 pin configuration

Abstract: M74HC11P 74LS11 IC pin configuration M74HC11 74LS11 circuit diagram with voltage 4000B 74LS11 M74HC11DP Mitsubishi 74LS11 CMOS 74LS11
Contextual Info: M I T S U B I S H I HIGH S P E E D C M O S M 74H C11P M 74H C11D P T R I P L E 3 -IN P U T P O S I T I V E AND G A T E DESCRIPTION PIN T he M74HC11 is a sem iconductor integrated circuit con­ CONFIGURATION TOP VIEW sisting of th re e 3-in put po sitiv e -lo g ic AND, usable as ne ga­

74hc112

Contextual Info: M54HC112 M74HC112 SCSTHOMSON m DUAL J-K FLIP FLOP WITH PRESET AND CLEAR a HIGH SPEED fMAX = 59 MHz Typ. at VCC= 5V LOW POWER DISSIPATION lCC = 2 (iA at Ta = 25°C • HIGH NOISE IMMUNITY VNIH = VNIL= 28% Vcc (MIN.) ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS

M74HC11

Abstract: M74HC11B1R M74HC11M1R M74HC11RM13TR M74HC11TTR TSSOP14
Contextual Info: M74HC11 TRIPLE 3-INPUT AND GATE • ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 9ns TYP. at VCC = 6V LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN)

Contextual Info: MITSUBISHI HIGH SPEED CMOS M74HC113P/FP/DP DUAL I -K F L IP -F L O P WITH S E T DESCRIPTION T he M 7 4 H C 1 1 3 is a sem ico n d u cto r integrated circu it co n ­ PIN CON FIGURATIO N TOP VIEW sistin g of of tw o n e g a tiv e -e d g e trig g ered J - K flip flops with

or gate thruth table

Contextual Info: M54HC113 M74HC113 Æ 7 SCS-THOM SON ^ 7 # R if lQ ^ Q i[ L [ l( g ir [S @ M D ( g i DUAL J-K FLIP FLOP WITH PRESET • HIGH SPEED fMAX= 64 MHz (Typ.) at V c c = 5 V LOW POWER DISSIPATION ICC = 2 at TA = 25° C ■ HIGH NOISE IMMUNITY VniH = V n il= 28% VCc (MIN.)

74HC112

Contextual Info: MI TSUBI SHI HIGH S P E E D C M OS M74HC112P DUAL l - K F L I P - F L O P WI TH S E T AND R E S E T DESCRIPTION The M 74H C 112 is a sem iconductor inte grated c ircu it con­ PIN CONFIGURATION TOP VIEW sisting of tw o n e g a tiv e -e d g e trig g e re d J -K flip flops with in­

Contextual Info: M ITSUBISHI HIGH S P E E D CM O S M74HC11P M74HC11DP T R IP L E 3 -IN P U T P O S IT IV E AND GATE DESCRIPTION The M74HC11 is a sem iconductor inte grated c ircu it con­ PIN CONFIGURATION TOP VIEW sisting of th re e 3-in put po s itiv e -lo g ic AND, usable as ne ga­

8 pin dip j k flipflop ic

Abstract: M74HC113 M74HC113B1R M74HC113M1R M74HC113RM13TR M74HC113TTR TSSOP14 jk flip flop
Contextual Info: M74HC113 DUAL J-K FLIP FLOP WITH PRESET • ■ ■ ■ ■ ■ ■ HIGH SPEED : fMAX = 79MHz TYP. at VCC = 6V LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN)

Contextual Info: M ITSU B ISH I HIGH SPEED CMOS M74HC112P/FP/DP DUAL i-K F L IP -F L O P W ITH S E T AND R ESET DESCRIPTION T h e M 7 4 H C 1 1 2 is a s e m ic o n d u c to r in te g ra te d c irc u it c o n ­ PIN CONFIGURATION TOP VIEW s is tin g of tw o n e g a t iv e - e d g e tr ig g e r e d J - K flip flo p s w ith in ­

54HC11

Contextual Info: S G S -T H O M S O N M54HCi R ffl0» [iyiM !0 gi M74HC11 i TRIPLE 3-INPUT AND GATE • HIG HSPEED tpD = 7 ns (TYP.) AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 1 |iA (MAX.) A T T a = 25°C ■ HIGH NOISE IMMUNITY V nih = V n il = 28 % V cc (MIN.) ■ OUTPUT DRIVE CAPABILITY

M74HC11

Abstract: M74HC11B1R M74HC11M1R M74HC11RM13TR M74HC11TTR TSSOP14
Contextual Info: M74HC11 TRIPLE 3-INPUT AND GATE • ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 9ns TYP. at VCC = 6V LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN)

74hc113

Abstract: or gate thruth table 54HC 74HC M54HC113 M74HC113
Contextual Info: Æ 7 SGS-THOMSON Ä 7# M54HC113 M74HC113 [ M lO g ^ [ i[ L [ l( g ,F [ ^ © l i O ( g S DUAL j - k f l ip f l o p w it h p r e s e t • HIGH SPEED fMAX= 64 MHz (Typ. at V q c = 5V LOW POWER DISSIPATION Ic e = 2 iiA at Ta = 2 5 °C i HIGH NOISE IM M U N ITY

74LS11 circuit diagram with voltage

Abstract: 74hc11
Contextual Info: M54HC11 M74HC11 SGS-THOMSON TRIPLE 3-INPUT AND GATE HIGH SPEED tPD = 10 ns TYP. at VCc = 5V LOW POWER DISSIPATION Ice = 1 (MAX.) at Ta = 25°C HIGH NOISE IMMUNITY = 28% V cc (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS V N IH = V N IL SYMMETRICAL OUTPUT IMPEDANCE

74HC112 pin diagram

Abstract: 74ls112 function table 74HC112
Contextual Info: M54HC112 M74HC112 SGS-THOMSON G L ì[LI TF[^ 5 RQ0© i DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • HIGH SPEED fMAX= 59 MHz (Typ.) at VCC= 5V LOW POWER DISSIPATION Icc = 2 at TA = 25°C ■ HIGH NOISE IMMUNITY V nih = V Nil = 28% Vcc (MIN.) ■ OUTPUT DRIVE CAPABILITY

PO13H

Abstract: TSSOP16 M74HC112 M74HC112B1R M74HC112M1R M74HC112RM13TR M74HC112TTR
Contextual Info: M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • ■ ■ ■ ■ ■ ■ HIGH SPEED : fMAX = 79MHz TYP. at VCC = 6V LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:

M74HC113

Abstract: M74HC113B1R M74HC113M1R M74HC113RM13TR M74HC113TTR TSSOP14 8 pin dip j k flipflop ic
Contextual Info: M74HC113 DUAL J-K FLIP FLOP WITH PRESET • ■ ■ ■ ■ ■ ■ HIGH SPEED : fMAX = 79MHz TYP. at VCC = 6V LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN)

M74HC11

Abstract: M74HC11B1R M74HC11M1R M74HC11RM13TR M74HC11TTR TSSOP14
Contextual Info: M74HC11 TRIPLE 3-INPUT AND GATE • ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 9ns TYP. at VCC = 6V LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN)

T flip flop IC

Abstract: JK flip flop IC diagram M74HC112 M74HC112B1R M74HC112M1R M74HC112RM13TR M74HC112TTR PO13H TSSOP16
Contextual Info: M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • ■ ■ ■ ■ ■ ■ HIGH SPEED : fMAX = 79MHz TYP. at VCC = 6V LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:

Contextual Info: M54HC11 M74HC11 A 7# Rii]D g^(Q ILi Tr[E(Q)lR!]0©i Æ 7 S G S - T H O M S O N TRIPLE 3-INPUT AND GATE • HIGH SPEED tpo = 10 ns (TYP.) at V c c = 5V ■ LOW POWER DISSIPATION Ice = 1 /*A (MAX.) at TA = 25°C ■ HIGH NOISE IMMUNITY V nih = V n il = 2 °/° ^CC (MIN.)

RS flip flop IC

Abstract: RS flip flop cmos Toggle flip flop IC 4000B 74LS114 M74HC114P JK flip flop IC "J-K Flip flops"
Contextual Info: M IT S U B IS H I HIGH S P E E D C M O S M74HC114P D U A L l- K F L IP -F L O P W IT H S E T AND C O M M O N R E S E T DESCRIPTION The M 74H C 114 is a sem iconductor integrated circu it con­ PIN CONFIGURATION TOP VIEW sisting of tw o n e g a tiv e -e d g e trig g e re d J-K flip flops with in­

RS flip flop cmos

Abstract: 74ls112 pin configuration FLIP FLOP RS 74ls112 pin diagram RS flip flop 74ls112 function table T flip flop IC 4000B 74LS112 M74HC112
Contextual Info: MI TSUBI SHI HIGH S P E E D C M OS M74HC112P DUAL i - K F L I P - F L O P WI TH S E T AND R E S E T DESCRIPTION The M 74H C 112 is a sem iconductor inte grated circuit con­ PIN CONFIGURATION TOP VIEW sisting of tw o n e g a tiv e -e d g e trig g e re d J -K flip flops with in­

74hc113

Abstract: T flip flop IC Toggle flip flop IC "J-K Flip flop" LS113 M74HC113B1R M74HC113C1R M74HC113M1R M54HC113 M54HC113F1R
Contextual Info: M54HC113 M74HC113 DUAL J-K FLIP FLOP WITH PRESET . . . . . . . . HIGH SPEED fMAX = 71 MHz TYP. at VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA at TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE

54HC

Abstract: 74HC M54HC11 M74HC11 74HC 84 B1-M74HC11
Contextual Info: HS-CMOS M54HC11 M74HC11 INTEGRATED CIRCUITS o PRELIMINARY DATA TRIPLE 3-INPUT AND GATE D ES C R IPTIO N The M54/74HC11 is a high speed C M O S T R IP L E 3-INPUT AND G A T E fabricated in silicon gate C 2M O S technology. It has the same high speed performance of L S T T L combined with true C M O S

Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M74HC114P DUAL l-K F L IP -F L O P W IT H S E T AND COMMON R ESET DESCRIPTION The M 74H C 114 is a sem iconductor integrated circu it con­ PIN CONFIGURATION TOP VIEW sisting of tw o n e g a tiv e -e d g e trig g e re d J -K flip flops with in­