DIGITAL DELAY LINES Search Results

AUDIO DELAY CIRCUIT DIAGRAM

Abstract: NJU26904 audio delay NJU26904V-C2 JESD65
Contextual Info: NJU26904 Digital Audio Delay • General Description ■Package The NJU26904 offers digital audio delay. The NJU26904 has internal delay memory. Delay function can adjust output time of a six-channel signal. This delay functions are suitable for delay time adjustment such as Audio

Contextual Info: NJU26904 Digital Audio Delay Package General Description The NJU26904 offers digital audio delay. The NJU26904 has internal delay memory. Delay function can adjust output time of a six-channel signal. This delay functions are suitable for delay time adjustment such as Audio

RCD Components

Abstract: A0805 A1405 A1410 MIL-D-83532 SA0805
Contextual Info: ACTIVE DIGITAL DELAY LINES RESISTORS "CAPS & COILS "DELAY LINES A0805 SERIES 5-TAP 8-PIN DIP SA0805 SERIES 5-TAP 8-PIN SIP A1405 SERIES 5-TAP 8-PIN DIP A1410 SERIES 10-TAP 14-PIN DIP Wide selection of sizes! RCD’s digital delay lines have been designed to provide precise tap

Contextual Info: ACTIVE DIGITAL DELAY LINES R ESSTO RS *CM>S&COILS -DELAY LINES A01 SERIES (SINGLE DELAY) A03 SERIES (TRIPLE DELAY) FEATURES □ □ □ □ □ Economical cost, prompt delivery! Wide range of values, 10nS to 500nS. TTL compatible Operating temperature: 0°C to 70°C

M 5218A

Abstract: m50194ap 5218A 5218AP 5218a 90 h m50194 Ic 5218a Echo Processor IC delay
Contextual Info: MITSUBISHI SOUND PROCESSOR ICs M65841SP DIGITAL REVERBE DIGITAL DELAY DESCRIPTION The M65841SP is an IC to generate reverberation effect. With synthesized outputs fo r five digital delay lines, this IC is capable o f producing the same reverberation e ffe c t as that in a church and bathroom, and is suitable fo r application

Contextual Info: Multiple Digital Delay Units SER|ES; MDU-14 w 24 pins DIP 10 0 K E C L Interfaced data delay devices. me. Features: • Input & output buffered. ■ 4 delay lines/package. ■ Compatible with ECL circuits. S pecificatio ns: ■ Total delay tolerance: ± 5 % or 1 ns

Yamaha oversampling filter

Abstract: YM7128B-F YM7128B Yamaha 716
Contextual Info: YAMAHAL 5 f YM 712BB Surround Processor S P 2 • OUTLINE This is an LSI which has quality digital surround sound capabilities realized by Y am aha’s digital audio technology. The LSI has built-in A/D and D/A converters which enable digital surround sound processing for analog input/output. Its eight digital delay lines m ay provide delay tim e of

ecl 10K

Abstract: RCD Components E1001 E1004 E1008 E103 E105 SCHEMAT
Contextual Info: PRELIMINARY ECL DIGITAL DELAY LINES -5-41-5 - ECL 10K INTERFACED -5-41-5 - ECL 100K INTERFACED FEATURES TYPE E105 - ECL 10K 5 TAP Tap Delay nS 3 20 4 25 5 30 6 2X Total Delay Pulse Spacing 5X Total Delay -1.0V provided by open emitter ECL 10K gate

Contextual Info: Multiple Digital Delay Unite W lllto SER|ES: MDU-12 16 pjns D|P 10KH ECl |ntertaced data delay \C devices;me. Features: • Input & output buffered. ■ 2 delay lines/package. ■ Fits in Standard 16 Pins DIP. S p e c ific a tio n s : ■ Total Delay To leran ce: ± 5 % or better,

srs wow

Abstract: NJU26100 NJU26103 QFP32-R1 I2S bus specification
Contextual Info: NJU26103 Digital Signal Processor for TV • General Description ■Package The NJU26103 is a high performance 24-bit digital audio processor for TV that has a QFP32-pin small package. The NJU26103 provides an internal delay memory to adjust the output delay

Contextual Info: Multiple Digital Delay U n itS SERIES: MDU-13 16 pins DIP 10 K H E C L Interfaced data (m delay devices; me. Features: • Input & Output Buffered. ■ 3 Delay lines/package. ■ Fits in Standard 16 Pins DIP. S p e c ific a tio n s : ■ Total Delay T o leran ce: ± 5 % or better,

MASW2040

Contextual Info: GaAs DPDT Switch DC - 2 GHz MASW2040 V 2.00 ● ● ● ● ● Cascadable Low Insertion Loss Low DC Power Consumption Low Distortion Operation Quiet Mode Useful as a Building Block for – Digital – Digital – Digital – Digital Attenuators Delay Lines

Contextual Info: GaAs DPDT Switch D C -2 GHz • • • • • MASW2040 RFA1 Cascadable Low Insertion Loss Low DC Power Consumption Low Distortion Operation Quiet Mode Useful as a Building Block for - Digital Digital Digital Digital A B RF1 Attenuators Delay Lines Phase Shifters

Contextual Info: 7 4 B b 3 4 b G 0 Q G 7 b ci bl4 • RCD ACTIVE DIGITAL DELAY LINES SERIES A01 - SINGLE DELAY SERIES A03 - TRIPLE DELAY ■ ■ ■ ■ ■ Economical cost, prompt delivery! Wide varieties of values, 10nS to 500nS TTL compatible Operating temperature: 0 °C to 7 0°C

analog delay line

Contextual Info: Data Sheet Triple Skew-Compensating Video Delay Line with Analog and Digital Control AD8120 FEATURES GENERAL DESCRIPTION Corrects for unshielded twisted pair UTP cable skew Delay of up to 50 ns per channel High speed 200 MHz BW @ VOUT = 1.4 V p-p and 0 ns delay

vhdl code for loop filter of digital PLL

Abstract: vhdl code for Digital DLL XAPP132 vhdl code for All Digital PLL CLK180 SRL16 XAPP138 vhdl code for phase frequency detector vhdl code for phase shift free vhdl code for pll
Contextual Info: Application Note: Virtex Series R Using the Virtex Delay-Locked Loop XAPP132 v2.8 January 5, 2006 Summary The Virtex FPGA series offers up to eight fully digital dedicated on-chip Delay-Locked Loop (DLL) circuits providing zero propagation delay, low clock skew between output clock signals

SRL16

Abstract: XAPP132 CLK180 13100499
Contextual Info: Application Note: Virtex Series R Using the Virtex Delay-Locked Loop XAPP132 v.2.0 January 27, 2000 Summary The Virtex FPGA series offers up to eight fully digital dedicated on-chip Delay-Locked Loop (DLL) circuits providing zero propagation delay, low clock skew between output clock signals

MC100EP195

Abstract: SY89295U SY89296U SY89296UMG SY89296UMGTR SY89296UMI SY89296UMITR SY89296UTI SY89296UTITR
Contextual Info: SY89296U 2.5V/3.3V 1.5MHz Precision LVPECL Programmable Delay with Fine Tune Control Precision Edge General Description The SY89296U is a programmable delay line that delays the input signal using a digital control signal. The delay can vary from 3.2ns to 14.8ns in 10ps increments. Further,

digital delay lines

Contextual Info: ACTIVE DIGITAL DELAY LINES SINGLE, DUAL, TRIPLE, QUAD DELAYS A0 SERIES RoHS RESISTORS CAPACITORS COILS DELAY LINES Term.W is Pb-free and RoHS compliant Economical cost, prompt delivery! Wide range of values, 5nS to 500nS TTL schottky interfaced OPTIONS Opt.T= trailing edge design

Digital Delay Lines

Abstract: 03a a03 A03AG 03s 8pin SM DELAY LINES
Contextual Info: ACTIVE DIGITAL DELAY LINES SINGLE, DUAL, TRIPLE, QUAD DELAYS A0 SERIES RoHS RESISTORS CAPACITORS COILS DELAY LINES RCD A03AG 1 50NS Term.W is Pb-free and RoHS compliant Economical cost, prompt delivery! Wide range of values, 5nS to 500nS TTL schottky interfaced

SY89296L

Abstract: MIC100EP195 SY89295U SY89295UMG SY89295UMGTR SY89295UMI SY89295UTI SY89295UTITR SY89296U
Contextual Info: SY89295U 2.5V/3.3V 1.5GHz Precision LVPECL Programmable Delay General Description The SY89295U is a programmable delay line that delays the input signal using a digital control signal. The delay can vary from 3.2ns to 14.8ns in 10ps increments. In addition, the input signal is LVPECL, uses either a 2.5V

XAPP174

Abstract: CLK180 SRL16 x174-01
Contextual Info: Application Note: Spartan-II FPGAs R XAPP174 v1.1 January 24, 2000 Using Delay-Locked Loops in Spartan-II FPGAs Summary The Spartan -II family provides four fully digital dedicated on-chip Delay-Locked Loop (DLL) circuits, which provide zero propagation delay, low clock skew between output clock signals

Contextual Info: ACTIVE DIGITAL DELAY LINES RESISTORS *CAPS S C O tS •DELAY L WES A0805 SERIES 5-TAP 8-PIN DIP SA0805 SERIES 5-t a p 8-p in s ip A1405 SERIES 5-TAP 8-PIN DIP A1410 SERIES 10-t a p 14-p in d ip Wide selection of sizes! R C D ’s digital delay lines have been designed to provide precise tap

34A-100

Abstract: newport 31A - 5151 31A-5250 300C 31A-5501 Delay Modules Newport Components delays newport components
Contextual Info: bS'OlM'i 00001S5 T77 • NCLB DIGITAL DELAY MODULES 31 A, 34A Series 5 Tap and Triple Independent 14 Pin Moulded DIP NEWPORT COMPONENTS LTD MAE D - DUAL-IN-LINE PACKAGE TOP VIEW 3 4 A -S E R IE S description The 31A and 34A series of Digital Delay Modules are Schottky TTL buffered