DELAY Search Results

Contextual Info: TIEPAL10016P8-3C HIGH-PERFORMANCE ExCL mP A l CIRCUIT D 30 83. D EC E M B E R 1987 • ECL 100K PAL • High-Performance Operation Propagation Delay . . . 3 ns Max JT PACKAG E TOP VIEW I e e • • ■ - 2 2 0 mA Max • Replacement for 100K ECL Logic

PAL16L8 programming specifications

Abstract: TIBPAL16R4 TIBPAL16L8
Contextual Info: TIBPAL16L8-20M. TIBPAL16R4 20M, TIBPAL16R6 20M, TIBPAL16R8 20M TIBPAL 16L8-15C, TIBPAL16R4 15C, TIBPAL 16R615C, TIBPAL 16R8 15C HIGH-PERFORMANCE IMPACT PAL CIRCUITS FEBRUARY 1984-REVISED DECEMBER 1987 • High-Performance Operation Propagation Delay M Suffix . . . 20 ns Max

Contextual Info: y UC1711 UC3711 UNITRODE Dual Ultra High-Speed FET Driver 15ns Propagation Delay 1.5A Source or Sink Output Drive Operation with 5V to 35V Supply High-Speed Schottky NPN Process 8-PIN MINIDIP Package ABSOLUTE MAXIMUM RATINGS note 1 Input Supply Voltage, V c c . 40V

d2439

Abstract: p725
Contextual Info: MC3423 OVERVOLTAGE-SENSING CIRCUIT D2439, A P R IL 1978— RE V IS E D M A R C H 1988 * D OR P PACKAGE Separate Outputs for Crowbar and Logic Circuitry TOP VIEW Programmable Time Delay to Eliminate Noise Triggering TTL-Level Activation Isolated From Voltage-Sensing Inputs

ksy 11

Contextual Info: y UC1875/6/7/8 UC2875/6/7/8 UC3875/6/7/8 UNITRODE Phase Shift Resonant Controller FEATURES DESCRIPTION • Zero to 100% Duty Cycle Control • Programmable Output Turn-On Delay The UC1875 family of integrated circuits implements control of a bridge power stage by phase-shifting the switching of one half-bridge with respect

uc3825 design

Abstract: power supply design uc3825
Contextual Info: IN T E G R A T E D C IR C U IT S UC1825 UC2825 UC3825 U N IT R O D E High Speed PWM Controller DESCRIPTION Compatible with Voltage or Current Mode Topologies Practical Operation Switching Frequencies to 1MHz 50ns Propagation Delay to Output High Current Dual Totem Pole Outputs

tc183

Abstract: E17G tc183G TC163G TC180G single port RAM TC183e Toshiba TC8570
Contextual Info: TOSHIBA TC183G/ECMOS ASIC Family 3.0V/3.3V and 5.0V, 0.5nm1 TheTC183G/E eases the transition from 5V to 3V based systems. Benefits • Mixed 3.0/3,3V and 5V I/O 0.5 micron CMOS process with fast 230ps gate delay performance with the power savings of a 3V core

Contextual Info: IN T E G R A T E D C IR C U IT S UC1823 UC2823 UC3823 U N IT R Q D E High Speed PWM Controller FEATURES Com patible w ith Voltage or Current-M ode Topologies Practical O peration @ Switching Frequencies to 1.0MHz 50ns Propagation Delay to Output High C urrent Totem Pole O utput 1,5A peak

two 7485

Abstract: 74s852 74s85 ic 7485 SN74B5
Contextual Info: SN5485, SN54LS8S, SN54S85 SN7485, SN74LS85, SN74S85 4-BIT MAGNITUDE COMPARATORS MARCH 1974 - R EV ISED MARCH 19B8 TYPE TYPICA L POWER DISSIPATION TYPICA L DELAY 4-BIT WORDS S N 5 4 8 5 . S N 5 4 L S 8 5 , S N 5 4 S 8 5 . . . J OR W P A C K A G E SN 7485 . . . N PACKAGE

18n8

Contextual Info: T IB P A D 18N8-6C HIGH-PERFORMANCE PROGRAMMABLE AD D RESS DECODER/NAND ARRAY D 3 0 8 6 , DECEMBER 1 9 8 7 Very High Speed Address Decoder Ideal for Use w ith High Speed Processors I/O Propagation Delay: 6 ns Max • Suitable for High Speed N A ND-NAND Logic

D425G

Abstract: ACT21 SN74BCT2166
Contextual Info: SN74BCT2163, SN74BCT2164, SN74BCT2166 16K x 5 CACHE ADDRESS COMPARATORS/TAG RAMs SCHS012-D3513, JUNE 1990-REVISED NOVEMBER 1991 SN74BCT2163, SN74BCT2164 Fast Address to MATCH Delay. 12 ns Max FM PACKAGE CTOP VIEW ’BCT2163 Has Totem-Pole Match Output Q\*~

Contextual Info: 74AC11204 HEX INVERTER/CLOCK DRIVER D3427, O C TO B ER 1989 DW OR N PACKAGE Low-Skew Propagation Delay Specifications for Clock Driver Applications TOP VIEW 1Y[ 1 2Y [ 2 3Y [ 3 Flow-Through Architecture Optimizes PCB Layout * * * Package Options Include Plastic “Small

Contextual Info: S N 74AC T215 7 2K x 16 C A C H E A D D R E S S C O M PA R A TO R /D A TA RAM D3326, JANUARY 1990-REVlSED JUNE 1990 Fast A ddress to Match Delay . . . 20 ns Max FN PACKAGE TOP VIEW Totem -Pole and Open-Drain Match Outputs On-Chip Address/D ata Com parator

D2911

Abstract: bit-slice
Contextual Info: TMS2150A 512 x 8 CACHE ADDRESS COMPARATOR D2911, M A RCH 1 982-R E V IS E D SEP TE M B E R 1990 DW, JD, OR NT PACKAGE TOP VIEW ’ACT2150A is Recommended for New Designs RESET[ 1 U Fast Address to Match Valid Delay - Two Speed Ranges: 35 ns and 45 ns 512

RDA 8810

Abstract: mfm encoder tw 8826 smd K2F NRZ to MFM encoder ade vco stg 8810 tc8560 13/13/RDA+8810 13/13/RDA 8810
Contextual Info: HARD DISK CONTROLLER TC8563AF-88 Variable Frequency O scillator for Hard Disk 1. GENERAL DESCRIPTION The TC8563AF-88 is a single chip VFO developed for easy realization of a hard disk system together with the hard disk controller TC8560F. T his VFO has realization the multi-stage delay line,

PE-64352

Abstract: LT 7506 PE64352
Contextual Info: SN75061 DRIVER/RECEIVER PAIR WITH SQUELCH D 2 9 5 9 . JA N U A R Y 1 9 8 7 - REVISED JU LY 1 9 9 0 • IEEE 8 0 2 .3 1BASE5 Driver and Receiver • On-Chip Receiver Squelch w ith Adjustable Threshold N P AC K A G E ITO P V IE W D R D LA J£ 1 Adjustable Squelch Delay

SCAD002

Abstract: BCT2164
Contextual Info: SN74BCT2163, SN74BCT2164, SN74BCT2166 16K x 5 CACHE ADDRESS COMPARATORS/TAG RAMs _ D3513, JUNE 1990 — REVISED A U G U S T 1990 • Fast Address to MATCH Delay . . .12-ns Max • ’BCT2163 has Totem-Pole Match Output

SN74AS8088

Contextual Info: SN54AS808B, SN74AS808B HEX 2-INPUT AND DRIVERS SDAS018C- DECEMBER 1 9 8 2 - REVISED JANUARY 1985 • High Capacitlve-Drive Capability • Typical Delay Time of 3.2 ns C|_ = 50 pF and Typical Power Dissipation of Less Than 13 mW Per Gate • Package Options Include Plastic

up down counter truth table

Contextual Info: TOSHIBA TC74AC169 4-bit Binary Up/Down Counter Features: • High Speed: fmax = ?MHz typ. at V cc = 5V • Low Power Dissipation: lcc = 8nA (max.) at Ta = 25°C • High Noise Immunity: VN,H= V ML= 28% V cc (min.) • Symmetrical Output Impedance: • Balanced Propagation Delays: tpLH = W

2D 1002 integrated circuit

Contextual Info: SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 D D D TYPE TYPICAL PROPAGATION DELAY TIME MAXIMUM CLOCK FREQUENCY ’173 23 ns 35 MHz ’LS173A 18 ns 50 MHz description SN54173, SN54LS173A . . . J OR W PACKAGE

reset IC sot23

Contextual Info: XC61F Series ETR0202_004a Voltage Detectors, Delay Circuit Built-In •GENERAL DESCRIPTION The XC61F series are highly accurate, low power consumption voltage detectors, manufactured using CMOS and laser trimming technologies. A delay circuit is built-in to each detector.

Contextual Info: TPS77901, TPS77918, TPS77925, TPS77930 250-mA LDO REGULATOR WITH INTEGRATED RESET IN A MSOP8 PACKAGE SLVS283B – MARCH 2000 – REVISED MAY 2000 D D D D D D D D D D Open Drain Power-On Reset With 220-ms Delay 250-mA Low-Dropout Voltage Regulator Available in 1.8-V, 2.5-V, 3-V, Fixed Output

transistor marking YD 317

Abstract: STM6719TW 7sf3 STM6719SFB Marking STMicroelectronics year digit Z STM6720SV marking sj STM6777TW 7TG3 sot23-6 marking yj
Contextual Info: STM6717/6718/6719/6720 STM6777/6778/6779/6780 Dual/triple ultra-low voltage supervisors with push-button reset with delay option Features • Primary supply (VCC1) monitor. Fixed (factory-programmed) reset thresholds: 4.63 V to 1.58 V ■ Secondary supply (VCC2) monitor

Contextual Info: QuickSwitch Products QS316233 High-Speed CMOS QS3162233 QuickSwitch 32:16 Mux/Demux & c lu c T O R , iN c . FEATURES/BENEFITS DESCRIPTION • Enhanced N channel FET with no inherent diode to Vcc • 5£2 bidirectional switches connect inputs to outputs • Zero propagation delay, zero ground bounce