DECODE Search Results

54HC154

Contextual Info: SN54HC154, SN74HC154 LINE TO 16 LINE DECODERS/DEMULTIPLEXERS D 2 6 8 4 , DECEMBER 1 9 8 2 -R E V IS E D SEPTEMBER 1987 • Decodes 4 Binary-Coded Inputs into One of 16 Mutually Exclusive Outputs • Performs the Demultiplexing Function by Distributing Data From One Input to Any

Contextual Info: TOSHIBA TC74HC4514AP TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74HC4514AP 4 -TO - 16 LINE DECODER/LATCH The TC74HC4514A are high speed CMOS 4 - LINE TO 16 LINE DECODER WITH LATCHED INPUTs fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent

Contextual Info: TOSHIBA TC4028BP/BF/BFN TO SH IBA CM OS DIG ITAL INTEGRATED CIRCUIT SILICON M ONOLITHIC TC4028BP, TC4028BF, TC4028BFN Note The JEDEC SOP (FN) is not available in Japan TC4028B B C D -T O -D E C IM A L DECODER TC4028B is a BCD-to-DECIMAL decoder which converts BCD

TC74LCX138FS

Contextual Info: lu ^ m u H INTEGRATED TOSHIBA CIRCUIT TECHNICAL u iu i i m l iim i cvjt\M i t u O t\v.u tl TC74LCX138F, TC74LCX138FN TC74LCX138FS DATA SILICON MONOLITHIC TENTATIVE DATA LOW VOLTAGE 3-TO -8 LINE DECODER W ITH 5V TOLERANT INPUTS A N D OUTPUTS The TC74LCX138 is a high performance CMOS 3-to-8

74F138

Contextual Info: S N 5 4 F13 8 , S N 74 F13 8 3-LINE TO 8-LINE D EC O D ERS/D EM U LTIPLEXERS D2932, MARCH 1987 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems S N 54F138 . . . J PACKAGE SN 74F138 . . . D OR N PACKAGE TOP VIEW AC 1 U ,6 3 vcc

Contextual Info: SN74LVC137 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES SCAS340 - MARCH 1994 » EPIC Enhanced-Performance Implanted CMOS Submicron Process • Typical V o lp (Output Ground Bounce) D, DB, OR PW PACKAGE (TOP VIEW) A[ B[ c[ Ü2A [ S2B[ G1[

Contextual Info: TC74LVQ138F/FN/FS 3-TO-8 LINE DECODER T h e T C 7 4 L V Q 1 3 8 is a H ig h sp e e d C M O S D E C O D E R fa b ric a t e d w it h silic o n g a t e a n d d o u b le - la y e r m e ta l w ir in g C 2M O S t e c h n o lo g y . D e s ig n e d f o r u se in 3.3 V o lt system s, it a c h ie v e s h ig h

Contextual Info: TOSHIBA TC74HCT138AP/AF/AFN TO SHIBA CMOS D IG ITAL INTEGRATED CIRCUIT SILICON M O N O LIT H IC TC74HCT138AP, TC74HCT138AF, TC74HCT138AFN N o te The JEDEC SOP (FN) is n o t a v a ila b le in Japan 3 - T O -8 LINE DECODER The TC74HCT138A is a high speed CMOS 3 - to - 8 LINE

IC 4511B pin

Abstract: 7 SEGMENT LETTER DISPLAY COMMON CATHODE tlr332 TLR-332 TC74HC4511P
Contextual Info: TC74HC4511P/F TC74HC4511P/F BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER The TC74HC4511 is a high speed CMOS BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER fablicated with silicon gate C2MOS technology. It enables high speed latch and decode operation with identical pin connection and function to standard CMOS 4511B.

4T016

Abstract: tc4514 TC4515
Contextual Info: TC4514BP, TC4515BP TC4514BP TC4515BP C 2M O S DIG ITAL IN T E G R A T E D C IR C U IT S IL IC O N M O N O L IT H IC 4-BIT LATCH/4-T0-16 LINE DECODER Output Active High Option 4-BIT LATCH/4-T0-16 LINE DECODER (Output Active Low Option) TC4514BP and TC4515BP are decoders which convert 4

Contextual Info: UT54ACS 139/UT54ACTS 139 Radiation-Hardened Dual 2-Line to 4-Line Decoders/Demultiplexers PINOUTS FEATURES 16-Pin DIP Top View • Incorporates two enable inputs to simplify cascading and/or data reception • 1.2 1 radiation-hardened CMOS - Latchup immune

051b

Contextual Info: SN54F138, SN74F138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDFS051B - MARCH 1987 - REVISED JULY 1996 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems SN54F13 8 . . . J PACKAGE SN74F138. . . D OR N PACKAGE TOP VIEW u Incorporates Three Enable Inputs to

D3318

Contextual Info: 74AC11139 DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER D3318, JULY 1989 - R EV ISED APRIL 1993 * Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems * Incorporates Two Enable Inputs to Simplify Cascading and/or Data Reception

Contextual Info: SN74ALS137, SN74AS137, SN54ALS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES D2661, APRIL 1982 - REVISED M AY 1986 Combings Decoder and 3-Bit Addreis Latch SN54ALS137 . . . J PACKAGE SN74ALS137, SN74AS137 . . . D O R N PACKAGE Incorporates 2 Output Enables to Simplify

18n8

Contextual Info: T IB P A D 18N8-6C HIGH-PERFORMANCE PROGRAMMABLE AD D RESS DECODER/NAND ARRAY D 3 0 8 6 , DECEMBER 1 9 8 7 Very High Speed Address Decoder Ideal for Use w ith High Speed Processors I/O Propagation Delay: 6 ns Max • Suitable for High Speed N A ND-NAND Logic

74F139 equivalent

Contextual Info: TOSHIBA TC74ACT139 2-to-4 Line Decoder Features: • The TC74ACT139 is an advanced high speed CMOS 2-TO-4 LINE DECODER/DEMULTIPLEXER fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent

SN74F138

Contextual Info: SN54F138, SN74F138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDFS051 A - D2932, MARCH 1987 - REVISED OCTOBER 1993 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception

SN54ALS137

Contextual Info: SN74ALS137, SN74AS137, SN54ALS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES D2661, APRIL 1982 - REVISED MAY 1986 Combines Decoder and 3-Bit Address Latch Incorporates 2 Output Enables to Simplify Cascading SN54ALS137 . . . J PACKAGE SN74ALS137, SN74AS137 . . . D OR N PACKAGE

Contextual Info: TL16PNP100A STANDALONE PLUG-AND-PLAY PnP CONTROLLER SLLS200B - MARCH 1995 - REVISED MARCH 1996 PnP Card Autoconfiguration Sequence Compliant Supports TVvo Logical Devices Decodes 10-Bit I/O Address Location With Programmable 1-, 2-, 4-, 8-, 16-Byte Block

Contextual Info: TOSHIBA TC3W01F/FU TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON M O N O LITH IC TC3W01F, TC3W01FU 2-TO -3 LINE DECODER W IT H ENABLE The TC3W 01 is a high speed C2MOS 2 to 3 LINE D EC O D ER/DEM U LTIPLEXER fa b ricated w ith silicon g a te C2MOS tech n o lo g y.

82C11

Abstract: um82c11 82450 um82290 AN/parallel port 378
Contextual Info: I UMC UM82290 ~S S S S S S S S S sin9ie- ° hip Muiti-i/o y Features • An integrated chip of PC/AT serial/parallel add-on card. ■ Including 2 serial ports 82450 ■ Also including 1 print port (UM82C11) ■ And also I/O decoder included. General Description

042b

Contextual Info: 74AC11138 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS042B - MAY 1988 - REVISED A P R IL I 996 D, N, OR PW PACKAGE TOP VIEW Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Y1 [ 1 Y2 [ 2 Incorporates Three Enable Inputs to

Contextual Info: SN54LV138, SN74LV138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SC LS190P- FEBRUARY 19 9 3 - REVISED JULY 1996 EPIC Enhanced-Performance Implanted CMOS 2-fi Process Typical Vqlp (Output Ground Bounce) < 0.8 V at Vc c , Ta = 25°C SN54LV138. . . J OR W PACKAGE

Contextual Info: 74ACT11139 DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER SCASI 75A - SEPTEMBER 1991 - REVISED APRIL 1996 • Inputs Are TTL-Voltage Compatible • Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems D, N, OR PW PACKAGE TOP VIEW