DDD72B2 Search Results
DDD72B2 Datasheets Context Search
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Contextual Info: XC9536 In-System Programmable CPLD K X I L I N X June 1, 1996 Version 1.0 Preliminary Product Specification Features Power Management • • 5 ns pin-to-pin logic delays on all pins fQisiy to 125 MHz • • • 36 macrocells with 800 usable gates Up to 34 user I/O pins |
OCR Scan |
XC9536 36V18 DDD72b2 44-Pin TT4175T |