DATA CCU Search Results

D4711

Abstract: lf2246gc
Contextual Info: LF2246 11 x 10-bit I m a g e Filter □ 66 M H z Data and Coefficient Input and Com putation Rate □ Four 11 x 10-bit Multipliers with Individual Data and Coefficient Inputs and a 25-bit A ccum ulator □ User-Selectable Fractional or Integer Tw o's C om plem ent Data

Motorola transistors MRF 947

Abstract: trimpots 3296 transistor C5386 1n4740 2N5591 Motorola 2N5688 CQ 542 Transistor npn motorola equivalent transistor of 2sc3358 HB215/D ic cd 2399 gp
Contextual Info: Selector Guide 1 Discrete Transistor Data Sheets Amplifier Data Sheets Monolithic Integrated Circuit H Data Sheets mm Case Dimensions Cross Reference and Sales Offices 6 M MOTOROLA RF Device Data This publication presents technical information for the several product families that

MachXO3

Contextual Info: MachXO3 Family Data Sheet Advance DS1047 Version 1.1, July 2014 MachXO3 Family Data Sheet Introduction June 2014 Advance Data Sheet DS1047 Features  Solutions  Flexible On-Chip Clocking • Smallest footprint, lowest power, high data throughput bridging solutions for mobile applications

MC14499P application note

Abstract: wiring diagram audio amplifier ic 6283 era 555 MOTOROLA delta dvp plc communication cable wiring diagram siemens transistor manual 68000 MC68681 PROGRAMMING EXAMPLE DSP56200 SP5615 CORDED MOTOROLA CT2 Solid State Optoelectronics Data Book 1977
Contextual Info: Selection Guides Data Sheets Evaluation Kits Application Notes and Product Literature Glossary Handling and Design Guidelines Quality and Reliability Mechanical Data DATA CLASSIFICATION Product Preview This heading on a data sheet indicates that the device is in the formative stages or under

Contextual Info: O ctober 1990 PRELIMINARY ML2200 ML22Q8 *e,M icro Linear 12-Bit Plus Sign Data Acquisition Peripheral GENERAL DESCRIPTION FEATURES The ML2200 and ML2208 Data Acquisition Peripherals DAP are monolithic CMOS data acquisition subsystems. These data acquisition peripherals feature an input multiplexer, a

machxo3

Contextual Info: MachXO3 Family Data Sheet Advance DS1047 Version 1.0, June 2014 MachXO3 Family Data Sheet Introduction June 2014 Advance Data Sheet DS1047 Features  Solutions  Flexible On-Chip Clocking • Smallest footprint, lowest power, high data throughput bridging solutions for mobile applications

MHW721A2

Abstract: 13001 S 6D TRANSISTOR atv5030* motorola 2N5591 MOTOROLA 13001 6D TRANSISTOR BGY41 MHW710-1 construction linear amplifier 2sc1945 7119 amperex bf503
Contextual Info: Volume I Selector Guide 1 Discrete Transistor Data Sheets 2 Case Dimensions 3 Volume II Selector Guide Amplifier Data Sheets 5 Tuning, Hot Carrier and PIN Diode Data Sheets 6 Technical Information Case Dimensions 8 Cross Reference and Sales Offices 9 MOTOROLA RF DEVICE DATA

LF2246QC-33

Contextual Info: LF2246 11 x 10-bit Image Filter DESCRIPTION FEATURES □ 40 M H z Data and Coefficient Input and Com putation Rate □ Four 11 x 10-bit M ultipliers w ith Individual Data and Coefficient Inputs and a 25-bit A ccum ulator □ U ser-Selectable Fractional or

EF6854

Abstract: EF68A54CV EF68B54 EF6854CM EF6854CV 68A54 D1L28
Contextual Info: y THOMSON COMPOSANTS MILITAIRES ET SPATIAUX EF 6854 NMOS ADVANCED DATA LINK CONTROLER ADLC DESCRIPTION The EF 6854 ADLC performs the com plex MPU/data commu­ nication lin k function fo r the «Advanced Data Communica­ tion Control Procedure» (ADCCP), High-Level Data-Link

ST18932-core

Abstract: N530 XD FST
Contextual Info: FZJ * 71 SGS-THOMSON S T 18933 DATA SIGNAL PROCESSOR PRELIMINARY DATA THE ST18933 INCLUDES : • A ST18932-CORE CPU ■ 4KX 16-BIT DATA RAM ■ 8KX 16-BIT DATA ROM ■ 16K X 32-BIT PROGRAM ROM ■ A BOOTSTRAP LOGIC USED TO LOAD THE EXTERNAL PROGRAM MEMORY FROM

fr 3709 z

Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 02.3EA, June 2013 LatticeECP3 Family Data Sheet Introduction February 2012 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 02.4EA, September 2013 LatticeECP3 Family Data Sheet Introduction February 2012 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

ECP3EA

Abstract: LFE3-70EA-6FN672C LFE3-70EA-6FN672I lfe3-17ea-6fn484c lfe3 LFE3-17EA6FN484C LFE3-17EA
Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 01.8EA, April 2011 LatticeECP3 Family Data Sheet Introduction December 2010 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

Contextual Info: HSP50016 Semiconductor Data Sheet January 1999 Digital Down Converter Features The Digital Down Converter DDC is a single chip synthesizer, quadrature mixer and lowpass filter. Its input data is a sampled data stream of up to 16 bits in width and up to a 75 MSPS data rate. The DDC performs down

LFE3-17EA

Abstract: LFE3-35EA-6FN484C DS1021 ECP3-35 ECP3-95 16x4-Bit convolution encoders LFE335EA6FN484C LFE3-35EA-8FN484C LFE3-95EA-6FN484C
Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 01.9EA, July 2011 LatticeECP3 Family Data Sheet Introduction December 2010 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 02.5EA, February 2014 LatticeECP3 Family Data Sheet Introduction February 2012 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

ECP3EA

Abstract: LFE3-95EA-6FN484C Socket 1156 VID pinout DDR3 timing lfe3-17ea-6fn484c lfe3 LFE3-17EA6FN484C
Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 02.2EA, April 2012 LatticeECP3 Family Data Sheet Introduction February 2012 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 02.6EA, March 2014 LatticeECP3 Family Data Sheet Introduction February 2012 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 02.7EA, April 2014 LatticeECP3 Family Data Sheet Introduction February 2012 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

LFE3-150EA-8FN1156C

Abstract: LFE3-70EA-6FN672C lfe3-17ea-6fn484c lfe3 LFE3-17EA6FN484C LFE3-17EA
Contextual Info: LatticeECP3 Family Data Sheet DS1021 Version 02.0EA, November 2011 LatticeECP3 Family Data Sheet Introduction November 2011 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

LFE3-17EA

Abstract: DS1021 ECP3-35 ECP3-95 LFE3-17EA-7FN484C lfe370e6fn672i LFE3-70EA8FN672 lfe3-70e 4420 ba LFE3-70EA-7FN484C
Contextual Info: LatticeECP3 Family Data Sheet Preliminary DS1021 Version 01.6, March 2010 LatticeECP3 Family Data Sheet Introduction November 2009 Preliminary Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

LFE3-17EA-6FN484C

Abstract: LFE3-17EA-6FTN256C LFE3-17EA-7FTN256C LFE3-17EA-7FTN256I ECP3-150 ECP3-150EA LFE3-35EA-7FTN256C ECP3-35 LFE3-17EA-8FN484C LFE3-17EA6FN484C
Contextual Info: LatticeECP3 Family Data Sheet Preliminary DS1021 Version 01.5, November 2009 LatticeECP3 Family Data Sheet Introduction November 2009 Preliminary Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

Contextual Info: LatticeECP3 Family Data Sheet Preliminary DS1021 Version 01.6, March 2010 LatticeECP3 Family Data Sheet Introduction November 2009 Preliminary Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support

Contextual Info: ECP5 Family Data Sheet Preliminary DS1044 Version 1.2, August 2014 ECP5 Family Data Sheet Introduction August 2014 Preliminary Data Sheet DS1044 Features  Higher Logic Density for Increased System Integration  Pre-Engineered Source Synchronous I/O