D3A MARKING CODE Search Results

D3A transistor

Contextual Info: MC10E404, MC100E404 5 V ECL Quad Differential AND/NAND The MC10E404/100E404 is a 4-bit differential AND/NAND device. The differential operation of the device makes it ideal for pulse shaping applications where duty cycle skew is critical. Special design techniques were incorporated to minimize the skew between the upper

EP105

Abstract: MC100EP105 MC10EP105 QFN32 LQFP-32 footprint LQFP32 footprint
Contextual Info: MC10EP105, MC100EP105 3.3V / 5V ECL Quad 2−Input Differential AND/NAND Description The MC10/100EP105 is a quad 2−input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device,

ECL IC NAND

Contextual Info: MC10E104, MC100E104 5V ECL Quint 2-Input AND/NAND Gate The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be

MC100E404

Abstract: MC100E404FN MC100E404FNR2 MC10E404 MC10E404FN MC10E404FNR2 ECL IC NAND
Contextual Info: MC10E404, MC100E404 5VĄECL Quad Differential AND/NAND The MC10E404/100E404 is a 4-bit differential AND/NAND device. The differential operation of the device makes it ideal for pulse shaping applications where duty cycle skew is critical. Special design techniques were incorporated to minimize the skew between the upper

Contextual Info: MC10E157, MC100E157 5 V ECL Quad 2:1 Multiplexer The MC10E/100E157 contains four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select SEL inputs. The individual select control makes the devices well suited for random logic designs.

Contextual Info: resistors UR73 current sensing chip resistor EU features • • • • • Very low resistance, high precision reliability Utilization of thick film Low T.C.R. achieved ±100 ppm/°C Marking: Indigo body color with white marking Products with lead-free terminations meet EU RoHS

IC of XNOR GATE

Abstract: MC100E107 MC10E107 MC10E107FN
Contextual Info: MC10E107, MC100E107 5V ECL Quint 2-Input XOR/XNOR Gate Description The MC10E/100E107 is a quint 2-input XOR/XNOR gate. The function output F is the OR of all five XOR outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are

IC LM 3210

Abstract: MC100E157 MC10E157 MC10E157FN
Contextual Info: MC10E157, MC100E157 5 V ECL Quad 2:1 Multiplexer Description The MC10E/100E157 contains four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select SEL inputs. The individual select control makes the devices well suited for random logic designs.

EP105

Abstract: MC100EP105 MC100EP105FA MC100EP105FAR2 MC10EP105 MC10EP105FA MC10EP105FAR2
Contextual Info: MC10EP105, MC100EP105 3.3V / 5VĄECL Quad 2-Input Differential AND/NAND The MC10/100EP105 is a quad 2–input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device,

Contextual Info: MC10EP105, MC100EP105 3.3V / 5VĄECL Quad 2-Input Differential AND/NAND The MC10/100EP105 is a quad 2–input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device,

EP105

Abstract: MC100EP105 MC100EP105FA MC100EP105FAR2 MC10EP105 MC10EP105FA MC10EP105FAR2 marking CODE D2B
Contextual Info: MC10EP105, MC100EP105 3.3V / 5VĄECL Quad 2-Input Differential AND/NAND The MC10/100EP105 is a quad 2–input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device,

MC100E104

Abstract: MC10E104 MC10E104FN transistor j 127 ECL IC NAND
Contextual Info: MC10E104, MC100E104 5V ECL Quint 2-Input AND/NAND Gate Description The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be

ic xnor

Abstract: MC100E107 MC100E107FN MC100E107FNR2 MC10E107 MC10E107FN MC10E107FNR2
Contextual Info: MC10E107, MC100E107 5VĄECL Quint 2ĆInput XOR/XNOR Gate The MC10E/100E107 is a quint 2-input XOR/XNOR gate. The function output F is the OR of all five XOR outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be used.

marking CODE D2B

Abstract: MC100E104 MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 marking D3B ECL IC NAND
Contextual Info: MC10E104, MC100E104 5VĄECL Quint 2ĆInput AND/NAND Gate The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be

50 ohm resistor

Contextual Info: MC10E101, MC100E101 5V ECL Quad 4-Input OR/NOR Gate The MC10E/100E101 is a quad 4-input OR/NOR gate. The 100 Series contains temperature compensation. • 500 ps Max. Propagation Delay • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V • http://onsemi.com

socket 775 pinout

Contextual Info: MC10E158, MC100E158 5V ECL 5-Bit 2:1 Multiplexer The MC10E/100E158 contains five 2:1 multiplexers with differential outputs. The output data are controlled by the Select input SEL . The 100 Series contains temperature compensation. • • • • • •

Contextual Info: MC10E155, MC100E155 5V ECL 6−Bit 2:1 Mux−Latch The MC10E/100E155 contains six 2:1 multiplexers followed by transparent latches with single−ended outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic

Contextual Info: MC10E154, MC100E154 5V ECL 5-Bit 2:1 Mux-Latch The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on

Contextual Info: MC10E167, MC100E167 5V ECL 6-Bit 2:1 MUX-Register The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop outputs by a positive edge on CLK1 or CLK2 or both . A HIGH on

MC100E101

Abstract: MC100E101FN MC100E101FNR2 MC10E101 MC10E101FN MC10E101FNR2
Contextual Info: MC10E101, MC100E101 5VĄECL Quad 4ĆInput OR/NOR Gate The MC10E/100E101 is a quad 4-input OR/NOR gate. The 100 Series contains temperature compensation. • 500 ps Max. Propagation Delay • PECL Mode Operating Range: VCC= 4.2 V to 5.7 V • http://onsemi.com

LQFP-32 footprint

Abstract: MC100EP101 MC10EP101 QFN32
Contextual Info: MC10EP101, MC100EP101 3.3V / 5V ECL Quad 4−Input OR/NOR Description The MC10/100EP101 is a Quad 4−input OR/NOR gate. The device is functionally equivalent to the E101. With AC performance faster than the E101 device, the EP101 is ideal for applications requiring the

Ceramic Resistor 5W

Abstract: L 10M marking marking CODE D2B UR73D 1E 5W
Contextual Info: 1733 Reader's Spreads pg1-203:document 1/27/09 4:04 PM Page 34 UR73 resistors current sensing chip resistor EU features • • • • • • Very low resistance, high precision reliability Suitable for reflow and flow soldering Utilization of thick film

MC10E155

Abstract: MC10E155FN MC10E155FNR2 MC100E155 MC100E155FN MC100E155FNR2
Contextual Info: MC10E155, MC100E155 5VĄECL 6ĆBit 2:1 MuxĆLatch The MC10E/100E155 contains six 2:1 multiplexers followed by transparent latches with single-ended outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic

MC100E158

Abstract: MC10E158 MC10E158FN LM 3050 3.3
Contextual Info: MC10E158, MC100E158 5V ECL 5-Bit 2:1 Multiplexer Description The MC10E/100E158 contains five 2:1 multiplexers with differential outputs. The output data are controlled by the Select input SEL . The 100 Series contains temperature compensation. http://onsemi.com