D22 PACKAGE DIAGRAM Search Results

11l 60 xe

Abstract: SN75LVDS85 SN75LVDS81
Contextual Info: SN75LVDS82 FLATLINK RECEIVER S LLS 259A - NOVEMBER 1996 - REVISED JANUARY 1997 D Û Û PACKAGE 4 : 2 8 D a t a C h a n n e l E x p a n s i o n at u p to 2 2 7 . 5 TOP V IE W M i ll i on B y t e s p e r S e c o n d ( M b y t e s / s ) Throughput • D22 [ 1

SC11

Abstract: DSP56303 SC10 SC12 TDO 139
Contextual Info: SECTION 3 PACKAGING PIN-OUT AND PACKAGE INFORMATION This sections provides information about the available packages for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated for each package.

AA0301

Abstract: SC11 DSP56302 SC10 SC12 D-6108 D2083
Contextual Info: SECTION 3 PACKAGING PIN-OUT AND PACKAGE INFORMATION This sections provides information about the available package for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated. The DSP56302 is available in a144-pin Thin

logic diagram of 7432

Abstract: CI 7408 TTL 7486 7408 s.i 7408 FL 9014 7486 nor CI 74LS08 7408 fairchild 7432 TTL
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 D17 9S41 1^1 FH [iä| [vii Eòi [T| r»1 Vcc Vcc füi Fai np f i ! Föi lyi rn

CY7C425

Abstract: C4206 1DT7201 CY7C429-20DC CY7C420
Contextual Info: 4b E D CYPRESS SSflTbbS □ 0 0 7 1 1 7 5 OCYP CY7C420, CY7C421 CY7C424, CY7C425 CY7C428* CY7C429 SEMICONDUCTOR CYPRESS SEMICONDUCTOR Cascadeable 512 x 9 FIFO Cascadeable IK x 9 FIFO Cascadeable 2K x 9 FIFO 'T - 'A W • TTL compatible • Three-state outputs

MIL-STD-1835

Abstract: D22 PACKAGE DIAGRAM 40 PIN CERDIP D2 Package diagram D2 Package MIL-STD d 1835 D5011 cerdip cerdip 16 lead
Contextual Info: Package Diagram Ceramic Dual-In-Line Packages 16-Lead 300-Mil CerDIP D2 MIL-STD-1835 D-2 Config. A 18-Lead (300-Mil) CerDIP D4 MIL-STD-1835 D-6 Config. A 1 Package Diagram 20-Lead (300-Mil) CerDIP D6 MIL-STD-1835 D-8 Config. A 22–Lead (400–Mil) CerDIP D8

MIL-STD-1835

Abstract: sidebraze
Contextual Info: Package Diagrams Ceramic Dual-In-Line Packages 16-Lead 300-Mil CerDIP D2 MIL-STD-1835 D-2 Config. A 51-80027 18-Lead (300-Mil) CerDIP D4 MIL-STD-1835 D-6 Config. A 51-80028 1 Package Diagrams 20-Lead (300-Mil) CerDIP D6 MIL-STD-1835 D-8 Config. A 51-80029

HI401

Abstract: 7C196 CY7C194 CY7C195 CY7C196
Contextual Info: MbE D • asaibt.2 D D O b b b M 2 n CYP CYPRESS SEMICONDUCTOR CYPRESS W SEMICONDUCTOR Features Automatic power-down when deselected Output Enable ÖE feature (7CX95 and7C196) CMOS for optimum speed/power Highspeed — t^A = 25 ns Low active power — 880 mW

CY7C425-15JI

Abstract: 7C419
Contextual Info: 2 5 6 x 9 , 5 1 2 x 9 , 1K x 9, 2 K x 9 , 4 K x 9 C ascadable FIFO Features • 256 x 9,512 x 9,1,024 x 9,2048 x 9, and 4096 x 9 FIFO buffer memory • Dual-port RAM cell • Asynchronous read/write • High-speed 50.0-MHz read/write independent of depth/width

CY7C

Abstract: 432-30D C4206 4407C
Contextual Info: p v « *y 1 i. p X : CY7C419/21/25/29/3 - 256 x 9, 512 x 9, 1K x 9, 2K x 9, 4K x 9 Cascadable FIFO Features 256 x 9, 512 x 9, 1,024 x 9, 2048 x 9, and 4096 x 9 FIFO buffer memory Dual-port RAM cell Asynchronous read/write High-speed 50.0-M H z read/write independent of

Contextual Info: I /¿0/9U Revision: August 18, 1994 CY7C419/21/25/29/33 / CYPRESS 256x9,512x9, 1K x 9, 2Kx9, 4K x 9 Cascadable FIFO Functional Description Features • 256 z 9,512 x 9 ,1,024 x 9,2048 x 9, and 4096 x 9 FIFO buffer memory • Dual-port RAM cell • Asynchronous read/write

Y7C425

Abstract: 2561b B 503 Potentiometers U 2561B V0120 CY7C428-25PC uv led 365 CY7C419 CY7C428 CY7C429
Contextual Info: /U H £ U . I l/ ^ D / 9 U Revision: August 18,1994 CY7C419/21/25/29/33 • / C Y P R E S S 2 5 6x 9, 5 1 2 x 9, I K x 9, 2Kx9T 4K x 9 Cascadable FIFO Features Functional Description • 256 x 9,512 x 9,1,024 x 9,2048 x 9, and 4096 x 9 FIFO buffer memory • Dual-port RAM cell

Contextual Info: CY7C194 CY7C195 CY7C196 CYPRESS SEMICONDUCTOR Features Automatic power-down when deselected Output Enable OE feature (7C195 and 7C196) CMOS for optimum speed/power High speed — tAA = 25 ns Low active power — 880 mW Low standby power — 220 mW TTL-compatible inputs and outputs

Contextual Info: CY7B194 CY7B195 CY7B196 CYPRESS SEMICONDUCTOR • High speed — tM = 10 ns • BiCMOS for optimum speed/power • Low active power — 850 mW • Low standby power — 160 mW • Automatic power-down when deselected • O utput enable OE feature (CY7B195 and CY7B196 only)

CY7C199-20DC

Contextual Info: CYPRESS 4bE SEMICONDUCTOR asa%t>a » aoobba? 3 i CYP CY7C198 CY7C199 CYPRESS SEMICONDUCTOR 32,768 x 8 Static R/W RAM Features Functional Description • Automatic power-down when deselected • CMOS for optimum speed/power • Hlgb speed — 25 ns » Low active power

Contextual Info: CY7B194 CY7B195 CY7B196 PRELIMINARY CYPRESS SEMICONDUCTOR 65,536 x 4 Static R/W RAM Features Functional Description • High speed — tAA = 10 ns • BiCMOS for optimum speed/power • Low active power — 825 mW • Low standby power — 330 mW • Automatic power-down when

cl98

Abstract: cy7c198-45dc CY7C199-15LMB 7C199-12 7C199-15 CY7C198 CY7C199 cy7c199-15pc
Contextual Info: CYPRESS 4bE SEMICONDUCTOR asa%t>a aoobba? 3 i » CYP CY7C198 CY7C199 CYPRESS SEMICONDUCTOR 32,768 x 8 Static R/W RAM Features Functional Description • Automatic power-down when deselected • CMOS for optimum speed/power • Hlgb speed — 25 ns » Low active power

7c198

Abstract: CY7C198-55DMB 19835 CY7C198-15DMB
Contextual Info: CY7C198 _ CY7C199 CYPRESS " SEMICONDUCTOR 32,768 x 8 Static RAV RAM both LOW, data on the eight data input/ output pins I/Oo through I/O7 is written into the memoiy location addressed by the address present on the address pins (Ao through A 14). Reading the device is ac­

IR LFN

Abstract: CY7C161 CY7C162
Contextual Info: CYPRESS SEMI COND UCTOR MbE D H aSfl^bLE 5 I ICYP ODDbMM? Features • Automatic power-down when deselected • Transparent write 7061 • CMOS for optimum speed/power • Highspeed — 15 ns U a • Low active power — 633 mW ‘ • Low standby power

la25p

Abstract: CY7C161A CY7C162A range-26
Contextual Info: MOE D CY PR ESS S E M I C O N D U C T O R EH 250^2 DOOMfibH 0 B B C V P 7= tf-2> /0 CY7C161A CY7C162A CYPRESS SEMICONDUCTOR Features • Automatic power-down when dese­ lected • TVansparent write 7C161A • CMOS for optimum speed/power • High speed

CY7C161A

Abstract: CY7C162A CY7C161A-25DMB
Contextual Info: 1CY 7C16 2A CY7C161A CY7C162A 16K x 4 Static RAM with Separate I/O Features Easy memory expansion is provided by active LOW chip enables CE1, CE2 and three-state drivers. They have an automatic power-down feature, reducing the power consumption by 60% when deselected.

CY7C182

Contextual Info: CYPRESS SE MI CON DUCTOR 4fc,E D E3 2 5 0 ^ 2 D00bS7S 3 ESCYP CY7C182 CYPRESS SEMICONDUCTOR Features Functional Description • Fast access time — Commercial: 25/35/45 us max. — Military! 35/45/55 ns (max.) • Low power consumption — Active: 770 m ff (max.)

Contextual Info: CY7C161A CY7C162A 16Kx 4 Static RAM with Separate I/O Features • High speed • • • • • • into the memory location specified on the address pins Ao through A 1 3 . Reading the device is accomplished by tak­ ing the chip enables ( ^ Ei, ( ^ 2 ) LOW

CY7C161A

Abstract: CY7C162A
Contextual Info: CY7C161A CY7C162A 16K x 4 Static RAM with Separate I/O Features Easy memory expansion is provided by active LOW chip enables CE1, CE2 and three-state drivers. They have an automatic power-down feature, reducing the power consumption by 60% when deselected.