D-LINK 635 Search Results

Contextual Info: RS 454-6358 Inner height D 31 mm Double share single link joining construction with large anti-friction single-pin. Frames removable from inner radius. Vertical separators are available. Wide frames on outer radius offer good protection. Due to its design

Contextual Info: 1.8 x 3.8mm Rectangular Low Profile u e d RJ45 Port Status Indicator LEDs ’ Features Applications Options • Each LED Shielded from • Transmit/Receive, Link Status View at Each Port Adjacent LEDs • Modems • Super Bright LEDs • Status Indicators

Contextual Info: B Ï U TECHNOLOGIES D L ÎC 2 Û 4 0 45E D 01 11Ô50Ô3 Q0QQQH7 M BIBTDT T ra ra s c e a ^ e s r FIBER OPTIC DATA LINK Features: Applications: • Full FDDI compliance • Compatible with 4-row industry standard pin-out • Single piece integrated FDDI transmitter/

spectran

Abstract: BD 266 S HFBR-25X4
Contextual Info: WBi HEWLETT* mLUM P A C K A R D 10 Megabaud Versatile Link Fiber Optic Transm itter and R eceiver for 1 mm POF and 200 |nm HCS HFBR-0508 Series HFBR-1528 Transm itter HFBR-2528 Receiver Technical Data Features Applications • Data Transmission at Signal

BT-8

Contextual Info: ^ B T & » TECH NOL OGIES &Z?4i 4SE D 116SQA3 0G0DG42 S BiBTDT '*"< 3 T E C H N O L O G I E S T - m - 91 D L K 2 0 0 0 T r a n s c e iv e r FIBER OPTIC DATA LINK Features: Applications: • Full FDDI compliance • FDDI systems • Single piece integrated FDDI transmitter/

Contextual Info: CM OS M anchester Encoder-D ecoder P in o u ts In the Repeater mode, the MED accepts Manchester code Input and recon­ structs it with a recovered clock. This minimizes the effects of noise on a serial data link. A digital phase lock loop generates the recovered clock. A

LVC16541

Contextual Info: 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS, 5 VOLTTOLERANT I/O DESCRIPTION: FEATURES: - Typical tsK o (O utput S kew ) < 2 5 0p s E S D > 2 0 0 0 V per M IL -S T D -8 8 3 , Method 3 0 1 5 ; > 2 0 0 V using m achine model (C = 2 0 0 p F , R = 0) 0 .635m m pitch S S O P , 0.5 0 m m pitch T S S O P

a 6351

Abstract: paradyne 8610 SHDSL configuration Paradyne 8820 SHDSL modems up/LG 6351
Contextual Info: Hotwire 8312/8314 ReachDSL Subscriber Line Cards 6310/6350/6351 ReachDSL Modems/Router F E AT U R E S • Provides consistent delivery of broadband services regardless of copper condition: — Long loops — Poor quality loops — Bad premises wiring

NK 637

Abstract: b 537 ADSP-21160 EM10 GP10 AT-637 AOS PACKING
Contextual Info: &21752/67$7865(*,67(56 Figure E-0. Table E-0. Listing E-0. 2YHUYLHZ This appendix provides bit definitions for the ADPS-21160’s control and status registers. Some of the registers are located in the processor core; these are called system registers, a subset of the processor’s universal register set. The core processor system registers are MODE1, MODE2,

NCR92C02A

Abstract: 35TH NCR asic mau aui NE521 P802 NCR SCSI cxb 100 transformer
Contextual Info: i ? ima M l C l P NCR92C02A Ethernet Twisted Pair Transceiver FEATURES Digital Im plem entation of IE E E 802.3 10B A SE-T Media A ttachm ent U nit M A U . Synchronous design for embedded M AU applications. Digital Equalization C ontrol for use with external summing resistors.

Zippy

Abstract: atx12v Zippy Technology AT8LK LAN Toner Kit 6350p R2G-6350P power supply 350W 350w 350w atx atx 350w
Contextual Info: Emacs/Zippy R2G-6350P 350W ATX12V Redundant Power Supply for 2U Chassis . Page 1 of 2 Sunday, July 09 2006 9:04:53 AM 0 Items In Cart Total: $0.00 Call toll free: 1-888-3464688 Monday-Friday 9am-6pm Eastern Raleigh Area : 919-5105464 Enter Keywords Here [Alt+S]

RXB38

Abstract: BMS 13-48 bus arbitration protocol super harvard architecture block diagram ADSP-21000 A-18 ADSP-21060 ADSP-21061 ADSP-21062 ADSP-2106X
Contextual Info: Contents CHAPTER 1 INTRODUCTION 1.1 OVERVIEW .1-1 1.2 ADSP-21000 FAMILY FEATURES & BENEFITS .1-5 1.2.1 System-Level Enhancements .1-6

R2528

Contextual Info: ¥hp% H EW LETT 1 M M PA CKARD 10 Megabaud Versatile Link Fiber Optic Transmitter and Receiver for 1 mm POF and 200 |im HCS HFBR-0508 Series HFBR-1528 Transmitter HFBR-2528 Receiver Technical Data Features Applications • Data Transmission at Signal Kates o f dc to 10 MBd

l1206

Abstract: l1303 L1119 HC12 L1001 L1003 L1004 L1005 L1007 L1110
Contextual Info: MCUEZLINK/D August 1997 MCUez LINKER USER’S MANUAL Copyright 1997 HIWARE AG; All Rights Reserved Important Notice to Users While every effort has been made to ensure the accuracy of all information in this document, Motorola assumes no liability to any party for any loss or damage caused by errors or omissions or

L1100

Abstract: L1106 L1103 l1303 HC12 L1110 M6805 HC05 HC08 L1115
Contextual Info: Freescale Semiconductor, Inc. MCUEZLNK0508/D Freescale Semiconductor, Inc. February 1998 MCUez LINKER USER'S MANUAL Copyright 1998 MOTOROLA and HIWARE AG; All Rights Reserved For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

VFL700

Abstract: VFL 683 visible light communication
Contextual Info: fiber.book : sec10.2.fm Page 10 Thursday, June 22, 2000 11:40 AM VFL700 Visible Fault Locator The Visible Fault Locator VFL is a 635nm laser source designed to be used to locate connections, bends, splices and cuts which increase the loss in the fiber path. Problem areas in the fiber path

HPR25

Abstract: AM79C901 circuit diagram of new holland fx 58
Contextual Info: P R E L IM IN A R Y AMD£I Am79C901 HomePHY1" Single-Chip 1/10 Mbps Home Networking PHY DISTINCTIVE CHARACTERISTICS • Fully integrated 1 Mbps HomePNA Physical Layer PHY as defined by Home Phoneline Networking Alliance (HomePNA) specification 1.1 — Optimized for home networking applications

B1137

Abstract: 2n2 f250 branch metric viterbi algorithm Convolutional Encoder TMS320C6416 Transistor y2n TMS320C6000 TR45
Contextual Info: Application Report SPRA750D - September 2003 Using TMS320C6416 Coprocessors: Viterbi Coprocessor VCP Jelena Nikolic-Popovic Digital Signal Processing Solutions ABSTRACT Viterbi Coprocessor (VCP) is a programmable peripheral for decoding of convolutional

chn 542

Contextual Info: xr XRT86VL32 PRELIMINARY DUAL T1/E1/J1 FRAMER/LIU COMBO FEBRUARY 2005 REV. P1.0.3 GENERAL DESCRIPTION The XRT86VL32 is a two-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .

DMO 565 R

Abstract: SCR PIN CONFIGURATION CHN 035 tp 147
Contextual Info: xr XRT86VL34 PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO JUNE 2005 REV. P1.0.4 GENERAL DESCRIPTION The XRT86VL34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .

RxFr1544

Contextual Info: xr XRT86VL32 PRELIMINARY DUAL T1/E1/J1 FRAMER/LIU COMBO JUNE 2005 REV. P1.0.4 GENERAL DESCRIPTION The XRT86VL32 is a two-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .

8 channel RC transmitter and Receiver circuit DIA

Abstract: CY7B923 CY7B933 RG-62 Siemens BIT Cypress VHDL alias 5 pin wire coupling
Contextual Info: t Frequently Asked Questions about HOTLink t The following questions are frequently asked by customers who are evaluating HOTLink products. These cursory answers will serve as an introduction for each topic. Separate application notes cover these topics in

DMO 565 R

Abstract: chn 656 chn 637 chn 547 CHN 549 dmo 265 CHN 922 equivalent CHN 632 CHN 645 chn 648 equivalent
Contextual Info: XRT86L34 PRELIMINARY PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO JUNE 2004 REV. P1.1.3 GENERAL DESCRIPTION The XRT86L34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L34 provides protection

DMO 565 R

Abstract: CHN 652 CHN 933 chn 539 W0104 CHN 628 CHN 523 chn 648 equivalent 3667 ict XRT86L34IB
Contextual Info: XRT86L34 PRELIMINARY PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO MAY 2004 REV. P1.1.1 GENERAL DESCRIPTION The XRT86L34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L34 provides protection