CYPRESS FLASH 370 TECHNOLOGY Search Results

Contextual Info: * CYPRESS ADVANCED INFORMATION CY7C375Ì UltraLogic 128-Macrocell Flash CPLD Features speed CPLDs. Like all members of the F lash 370 i family, the CY7C375i is de­ • 128 macrocells in eight logic blocks • 128 I/O pins • 6 dedicated inputs including 4 clock

Contextual Info: CY7C371 PRELIMINARY CYPRESS SEMICONDUCTOR 32-Macrocell Flash PLD Features Functional Description • 32 macrocells in two logic blocks T h e CY7C371 is a Flash E rasable Pro­ g ram m able Logic D evice E P L D and is p a rt o f th e FLA SH 370 family o f high-density, high-speed PLD s. Like all m em bers of

Contextual Info: ADVANCED INFORMATION f CYPRESS SEMICONDUCTOR 256-Macrocell Flash PLD Features Functional Description • 256 macrocells in 16 logic blocks T he CY 7C376 is a Flash E rasable Pro­ gram m able Logic D evice E P L D and is p a rt o f th e FLA SH 370 family o f high-density, high-speed PLD s. Like all m em bers of

Contextual Info: Features « 128 macrocells in eight logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • No hidden delays • High speed — fMAx = 100 MHz — tpo = 12 ns — ts = 7 ns " tco = 7 ns • Electrically Alterable Flash technology • Available in 84-pin PLCC, 84-pin

features cypress flash 370

Abstract: cypress flash 370 device cypress flash 370
Contextual Info: Revision: Monday, January 4,1993 57E D • 550=1^2 □ D D tlQ21 573 ■ CYP 07 CY7C373 C VPRESS SEMICONDUCTOR PRELIMINARY 7M CYPRESS SEMICONDUCTOR 64-Macrocell Flash PLD perform ance o f the 22V10 to high-density PLD s. Features • 64 m acrocells in four logic blocks

features cypress flash 370

Abstract: logic block diagram of cypress flash 370 device cypress flash 370 device cypress flash 370 cypress flash 370 technology cypress FLASH370 device cypress quickpro II cypress flash 370 device technology
Contextual Info: F la s h 3 7 0 T0 CYPRESS — Low-cost, text-based design tool, PLD compiler — IEEE 1076-compliant VHDL — Available on PC and Sun platforms • Warp3m CAE development system — VHDL input — ViewLogic graphical user interface — Schematic capture ViewDraw

cypress flash 370 device

Abstract: cypress flash 370 CPLD features cypress flash 370 cypress flash 370 logic block diagram of cypress flash 370 device cypress flash 370 technology cypress flash 370 device technology
Contextual Info: fax id: 6126 For new designs, see CY7C371L CY7C371 UltraLogic 32-Macrocell Flash CPLD of use and high performance of the 22V10 to high-density CPLDs. Featu res • 32 macrocells in two logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins

Contextual Info: PRELIMINARY C Y 7C 374i UltraLogic 128-Macrocell Flash CPLD Features • • • • 128 macrocells in eight logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology — JTAG interface • Bus Hold capabilities on all l/Os and dedicated inputs

architecture of cypress FLASH370 cpld

Abstract: cypress flash 370 cypress flash 370 device logic block diagram of cypress flash 370 device features cypress flash 370 architecture of cypress FLASH370 device cypress flash 370 CPLD cypress flash 370 device technology cypress FLASH370 logic
Contextual Info: fax id: 6130 1CY 7C37 5 For new designs see CY7C375i. CY7C375 UltraLogic 128-Macrocell Flash CPLD Features Functional Description • 28 macrocells in eight logic blocks The CY7C375 is a Flash erasable Complex Programmable Logic Device CPLD and is part of the FLASH370™ family of

319S2

Abstract: 7C375-83 CY7C375 FLASH370 25ab
Contextual Info: CY7C375 PRELIMINARY y CYPRESS 128-Macrocell Flash CPLD Features Functional Description • 128 macrocells in eight logic blocks • 128 I/O pins • 6 dedicated inputs including 4 clock pins • No hidden delays • High speed — fMAX = 100 MHz — tpD — 12 ns

cypress flash 370 CPLD

Abstract: features cypress flash 370 logic block diagram of cypress flash 370 device cypress flash 370 0117C
Contextual Info: 400-943-Z843-> 07/31/95 B9'i B7'ì Z7 16838B01932 Cypress Seniconducto Page B2B 7C37S: W ednesday September 23,1092 Revtalon: Thurvdty, June 1 8 ,1 M 4 CYPRESS 64-Macrocell Flash CPLD den q»ed delays such as fanout effects, in­ terconnect delays, or expander delays. Re­

cypress flash 370

Abstract: architecture of cypress FLASH370 device cypress flash 370 device architecture of cypress FLASH370 cpld CLCC 84 features cypress flash 370 CY7C373 CY7C374 FLASH370 CLCC 100
Contextual Info: fax id: 6129 1CY 7C37 4 For new designs see CY7C374i. CY7C374 UltraLogic 128-Macrocell Flash CPLD Features • • • • • Functional Description 128 macrocells in eight logic blocks 64 I/O pins 6 dedicated inputs including 4 clock pins No hidden delays

CY7C375I

Abstract: cypress flash 370 O103
Contextual Info: PRELIMINARY CY7C375i UltraLogict 128ĆMacrocell Flash CPLD D D D 128 macrocells in eight logic blocks D InĆSystem Reprogrammable ISRt Flash technology 128 I/O pins 5 dedicated inputs including 4 clock pins Bus Hold capabilities on all I/Os and dedicated inputs

C1573

Abstract: C0043
Contextual Info: Revision: Tuesday, December 22,1992 MAR ut WL* C 2 3 I993 CY7C375 PRELIMINARY CYPRESS SEMICONDUCTOR 128-Macrocell FLASH PLD Features Functional Description • 128 macrocells in eight logic blocks • 128 I/O pins • 6 dedicated inputs including 4 clock pins

319S2

Contextual Info: WFw CYPRESS CY7C374Ì ADVANCED INFORMATION UltraLogic 128-Macrocell Flash CPLD Features • 128 macrocells in eight logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • In-System Reprogrammable ISR™ Flash technology — JTAG interface

Contextual Info: CYPRESS SEMICONDUCTOR b5E » • ESñTbbS 001QS7Q CY7C375 PRELIMINARY CYPRESS SEMICONDUCTOR 128-Macrocell Flash PLD Features Functional Description • 128 macrocells in eight logic blocks • 128 I/O pins • 6 dedicated inputs including 4 clock pins • No hidden delays

Contextual Info: CY7C375 CYPRESS UltraLogic 128-Macrocell Flash CPLD Features Functional Description • 128 m acrocells in eight logic blocks • 128 I/O pin s T h e CY7C375 is a Flash erasable Com plex Program m able Logic D evice C PL D and is p a rt o f th e F lash 3 7 0 “ family o f highdensity, high-speed C PLD s. Like all m em ­

Contextual Info: '= CYPRESS CY7C372 UltraLogic 64-Macrocell Flash CPLD Features Functional Description • 64 macrocells in four logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins • No hidden delays • High speed - f M A X = 125 MHz The CY7C372 is a Flash erasable Complex

l041b

Abstract: I036
Contextual Info: CYPRESS CY7C375 PRELIMINARY 128-Macrocell Flash CPLD Features Functional Description • 128 macrocells in eight logic blocks • 128 I/O pins • 6 dedicated inputs including 4 clock pins • No hidden delays • High speed - f M A X = 100MHz — tpD = 12 DS

logic block diagram of cypress flash 370 device

Abstract: cypress flash 370 device SEM03 features cypress flash 370 7C371-2
Contextual Info: 7C373: Thursday, September 24,1992 .Revision: Monday,January4,1993 S7E D • 2 5 f l T L > t iE 00CH031 41E CYPRESS SEMICONDUCTOR ^ ^ s ts s s s 'Z ^ ^ i is m = ^ 'T'^' ci- PRELIMINARY Q Y PR ESS . • 128 macrocells in eight logic blocks

C1573

Abstract: sim 300
Contextual Info: Miuiouay, úo^ioiiiuvi tn, 199& Revision: Tuesday, December 22,1992 •fi»«* n i W «! S7E D 5 5 5 ^ 2 C YP RE S S SEMI CONDUCTOR ODDTOMl ICYP 3bl CY7C375 PRELIMINARY CYPRESS SEMICONDUCTOR 128-Macrocell FLASH PLD Features Functional Description • 128 macroceils in eight logic blocks

Contextual Info: CY7C374 PRELIMINARY y CYPRESS 128-Macrocell Flash CPLD Features • 128 macrocells in eight logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • No hidden delays • High speed — f M AX = 100 MHz — tpo = 12 ns — ts = 7 ns — t c o = 7 ns

Contextual Info: CY7C372 PRELIMINARY WFJ CYPRESS 64-Macrocell Flash CPLD Features Functional Description • 64 macrocells in four logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins • No hidden delays • Highspeed — fMAX = 125 MHz — tpD = 10 ns

Contextual Info: UltraLogic 128-Macrocell Flash CPLD is designed to bring th e ease o f use and high perform ance o f th e 22V10 to highdensity CPLDs. Features • 128 macrocells in eight logic blocks • 64 I/O pins T he 128 m acrocells in th e CY7C374 are di­ vided betw een eight logic blocks. Each