CY7C141 Search Results

bzx 850

Abstract: bzx 850 30
Contextual Info: CY7C1412AV18 CY7C1414AV18 36 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses

cy7c131-55nc

Abstract: ZT12 CY7C130 CY7C131 CY7C140 CY7C141 IDT7130 IDT7140
Contextual Info: CY7C130/CY7C131 CY7C140/CY7C141 W CYPRESS Features • 0.8-micron CMOS for optimum speed/power • Automatic power-down • TTL compatible • Capable o f withstanding greater than 2001V electrostatic discharge • Fully asynchronous operation • Master CY7C130/CY7C131 easily ex­

ebe switches

Abstract: CY7C130 CY7C131 CY7C140 CY7C141 7CJ41-25 7CI40-35
Contextual Info: CYPRESS SEMICONDUCTOR 00 0 3 4 2 1 EbE D 5 • CY7C130/CY7C131 CY7C140/CY7C141 -Z Z A Z . o y n p rrQ C 1024 x 8 Dual-Port Static RAM SEMICONDUCTOR Features Functional Description • 0,8-micron CMOS for optimum speed/power • Automatic power-down • TTL-compatible

Contextual Info: CY7C130/CY7C131 CY7C140/CY7C141 CYPRESS SEMICONDUCTOR Features Functional Description • 0.8-micron CMOS for optimum speed/power • Automatic power-down • TTL compatible • Capable of withstanding greater than 2001V electrostatic discharge • Fully asynchronous operation

Contextual Info: fax id: 5200 CY7C130/CY7C131 CY7C140/CY7C141 W CYPRESS 1K x 8 Dual-Port Static Ram Features Functional Description True Dual-Ported memory cells which allow simulta­ neous reads of the same memory location 1K x 8 organization 0.65-micron CMOS for optimum speed/power

Contextual Info: CY7C1413JV18 CY7C1415JV18 36-Mbit QDR II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1413JV18 – 2M x 18 ■ 300-MHz clock for high bandwidth ■ 4-word burst for reducing address bus frequency

CY7C130

Abstract: CY7C131 CY7C140 CY7C141
Contextual Info: CY7C130/CY7C131 CY7C140/CY7C141 1K x 8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 1K x 8 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 15 ns

C1307

Abstract: cY7c131 I CY7C130 CY7C131 CY7C140 CY7C141 C130-15 C1303 C13017
Contextual Info: fax id: 5200 1CY 7C14 0 CY7C130/CY7C131 CY7C140/CY7C141 1K x 8 Dual-Port Static Ram Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 1K x 8 organization • 0.65-micron CMOS for optimum speed/power

Contextual Info: CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 PRELIMINARY 36-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency

Contextual Info: CY7C1413BV18 CY7C1415BV18 36-Mbit QDR II SRAM 4-Word Burst Architecture 36-Mbit QDR® II SRAM 4-Word Burst Architecture Features • JTAG 1149.1 compatible test access port ■ Delay Lock Loop DLL for accurate data placement ■ Separate independent read and write data ports

CY7C1413JV18-300BZXC

Abstract: CY7C1415JV18-300BZXC CY7C1411JV18 CY7C1413JV18 CY7C1415JV18 CY7C1426JV18
Contextual Info: CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1411JV18 – 4M x 8 ■ 300 MHz clock for high bandwidth

CY7C1412BV18-200BZI

Abstract: CY7C1412BV18-250BZXC CY7C1412BV18-167BZI CY7C1410BV18 CY7C1412BV18 CY7C1414BV18 CY7C1425BV18 CY7C1412BV18-250BZC cy7c1414bv18-250bzxi
Contextual Info: CY7C1410BV18, CY7C1425BV18 CY7C1412BV18, CY7C1414BV18 36-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■

HD 46802

Abstract: CY7C1411AV18 CY7C1413AV18 CY7C1415AV18 CY7C1426AV18
Contextual Info: CY7C1411AV18, CY7C1426AV18 CY7C1413AV18, CY7C1415AV18 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth

3246A

Contextual Info: fax id: 5200 CY7C130/CY7C131 CY7C140/CY7C141 CYPRESS 1K x 8 Dual-Port Static RAM Functional Description Features True Dual-Ported memory ceils which allow simulta­ neous reads of the same memory location 1K x 8 organization 0.65-micron CMOS for optimum speed/power

Contextual Info: CY7C1412AV18 CY7C1414AV18 36 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses

Zl13

Abstract: ZL12 CY7C130 CY7C131 CY7C140 CY7C141 IDT7130 IDT7140 C1308 wj 75
Contextual Info: CY7C130/CY7C131 CY7C140/CY7C141 W CYPRESS Features • 0.8-micron CMOS for optimum speed/power • Automatic power-down • TTL compatible • Capable o f withstanding greater than 2001V electrostatic discharge • Fully asynchronous operation • Master CY7C130/CY7C131 easily ex­

IR 10e 3e

Contextual Info: CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 36-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports The CY7C1410AV18, CY7C1425AV18, CY7C1412AV18, and CY7C1414AV18 are 1.8V Synchronous Pipelined SRAMs,

Contextual Info: CY7C1410BV18, CY7C1425BV18 CY7C1412BV18, CY7C1414BV18 36-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■

Contextual Info: CY7C1418JV18 CY7C1420JV18 36-Mbit DDR II SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 2M x 18, 1M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces

Contextual Info: CY7C1417AV18 CY7C1428AV18 CY7C1419AV18 CY7C1421AV18 PRELIMINARY 36-Mbit DDR-II SRAM 4-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 • 300-MHz clock for high bandwidth • 4-Word burst for reducing address bus frequency

CY7C1425KV18

Contextual Info: CY7C1410KV18, CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 36-Mbit QDR II SRAM 2-Word Burst Architecture 36-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions

Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-12561 Spec Title: CY7C1425JV18/CY7C1412JV18/CY7C1414JV18, 36-MBIT QDR R II SRAM 2-WORD BURST ARCHITECTURE Sunset Owner: Anuj Chakrapani (AJU) Replaced by: None CY7C1425JV18 CY7C1412JV18 CY7C1414JV18 36-Mbit QDR II SRAM 2-Word Burst

CY7C1411AV18

Abstract: CY7C1413AV18 CY7C1415AV18 CY7C1426AV18
Contextual Info: CY7C1411AV18, CY7C1426AV18 CY7C1413AV18, CY7C1415AV18 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth

CY7C1413V18

Abstract: CY7C1415AV18 CY7C1415V18
Contextual Info: CY7C1411V18 CY7C1426V18 CY7C1413V18 CY7C1415V18 PRELIMINARY 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth