CY7C1312BV18 Search Results
CY7C1312BV18 Datasheets (12)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
|---|---|---|---|---|---|---|---|
| CY7C1312BV18 | 
 
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18-Mbit QDR-II SRAM 2-Word Burst Architecture | Original | 264.85KB | 23 | ||
| CY7C1312BV18-167BZC | 
 
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18-Mbit QDR -II SRAM 2-Word Burst Architecture | Original | 425.24KB | 29 | ||
| CY7C1312BV18-167BZC | 
 
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18-Mbit QDR-II SRAM 2-Word Burst Architecture | Original | 264.87KB | 23 | ||
| CY7C1312BV18-167BZCT | 
 
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18-Mbit QDR -II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 1.7 to 1.9 V | Original | 425.24KB | 29 | ||
| CY7C1312BV18-167BZI | 
 
 | 
18-Mbit QDR -II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 1.7 to 1.9 V | Original | 425.24KB | 29 | ||
| CY7C1312BV18-167BZXC | 
 
 | 
18-Mbit QDR-II SRAM 2-Word Burst Architecture | Original | 264.85KB | 23 | ||
| CY7C1312BV18-200BZC | 
 
 | 
18-Mbit QDR -II SRAM 2-Word Burst Architecture | Original | 425.24KB | 29 | ||
| CY7C1312BV18-200BZC | 
 
 | 
18-Mbit QDR-II SRAM 2-Word Burst Architecture | Original | 264.87KB | 23 | ||
| CY7C1312BV18-200BZI | 
 
 | 
18-Mbit QDR -II SRAM 2-Word Burst Architecture | Original | 425.24KB | 29 | ||
| CY7C1312BV18-200BZXC | 
 
 | 
18-Mbit QDR -II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 1.7 to 1.9 V | Original | 425.24KB | 29 | ||
| CY7C1312BV18-250BZC | 
 
 | 
18-Mbit QDR -II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 1.7 to 1.9 V | Original | 425.24KB | 29 | ||
| CY7C1312BV18-250BZC | 
 
 | 
18-Mbit QDR-II SRAM 2-Word Burst Architecture | Original | 264.87KB | 23 | 
CY7C1312BV18 Price and Stock
Infineon Technologies AG CY7C1312BV18-200BZIIC SRAM 18MBIT PARALLEL 165FBGA | 
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
 
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CY7C1312BV18-200BZI | Tray | 
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Buy Now | |||||||
Infineon Technologies AG CY7C1312BV18-250BZCIC SRAM 18MBIT PAR 165FBGA | 
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
 
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CY7C1312BV18-250BZC | Tray | 136 | 
  | 
Buy Now | ||||||
Infineon Technologies AG CY7C1312BV18-167BZCIC SRAM 18MBIT PAR 165FBGA | 
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
 
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CY7C1312BV18-167BZC | Tray | 136 | 
  | 
Buy Now | ||||||
Infineon Technologies AG CY7C1312BV18-167BZIIC SRAM 18MBIT PAR 165FBGA | 
|||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
 
 | 
CY7C1312BV18-167BZI | Tray | 
  | 
Buy Now | |||||||
Infineon Technologies AG CY7C1312BV18-200BZCIC SRAM 18MBIT PARALLEL 165FBGA | 
|||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
 
 | 
CY7C1312BV18-200BZC | Tray | 136 | 
  | 
Buy Now | ||||||
CY7C1312BV18 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
CY7C1310BV18
Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 
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 Original  | 
CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, CY7C1314BV18 CY7C1310BV18 CY7C1312BV18 CY7C1910BV18 | |
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 Contextual Info: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth  | 
 Original  | 
CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit 250-MHz | |
CY7C1312BV18
Abstract: CY7C1314BV18 CY7C1312 
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 Original  | 
CY7C1312BV18 CY7C1314BV18 CY7C1312BV18 CY7C1314BV18 CY7C1312 | |
CY7C1312BV18-167BZCContextual Info: CY7C1312BV18 CY7C1314BV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth  | 
 Original  | 
CY7C1312BV18 CY7C1314BV18 18-Mbit CY7C1312BV18, CY7C1314BV18 CY7C1312BV18-167BZC | |
CY7C1310BV18
Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 
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 Original  | 
CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit 250-MHz CY7C1310BV18 CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 | |
CY7C1310BV18
Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 static SRAM single port 
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 Original  | 
CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, CY7C1314BV18 CY7C1310BV18 CY7C1312BV18 CY7C1910BV18 static SRAM single port | |
| 
 Contextual Info: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth  | 
 Original  | 
CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit 250-MHz | |
| 
 Contextual Info: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth  | 
 Original  | 
CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit 250-MHz | |
| 
 Contextual Info: CY7C1312BV18 CY7C1314BV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth  | 
 Original  | 
CY7C1312BV18 CY7C1314BV18 18-Mbit CY7C1312BV18, CY7C1314BV18 | |
CY7C1310BV18
Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 CY7C1314BV18-167BZXI 
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 Original  | 
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 18-Mbit CY7C1310BV18 CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 CY7C1314BV18-167BZXI | |
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 Contextual Info: CY7C1310BV18 CY7C1312BV18 CY7C1314BV18 PRELIMINARY 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth  | 
 Original  | 
CY7C1310BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit 300-MHz CY7C1910BV18 BB165E BB165D | |
CY7C1338-100AXC
Abstract: gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC 
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 Original  | 
CY7C1019BV33-15VC GS71108AJ-12 CY7C1019BV33-15VXC GS71108AGJ-12 CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12 CY7C1019CV33-10VC GS71108AJ-10 CY7C1338-100AXC gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC |