CY7C09159V Search Results

A12L

Abstract: A13L CY7C09159V CY7C09169V
Contextual Info: fax id: 5208 CYPRESS CY7C09159V CY7C09169V PRELIMINARY 3.3V 8K/16K x 9 Synchronous Dual Port Static RAM • H ig h-speed clo ck to d ata ac ce ss 7.5/12 ns m ax. Features • 3.3V Low o p e ratin g p ow er • True D u al-P o rted m e m o ry cells w h ich allo w sim u lta­

CY7C09159V

Abstract: CY7C09169V
Contextual Info: fax id: 5208 51 CY7C09159V CY7C09169V PRELIMINARY 3.3V 8K/16K x 9 Synchronous Dual Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 2 Flow-Through/Pipelined devices — 8K x 9 organization CY7C09159V

Contextual Info: fax id: 5208 CYPRESS CY7C09159V CY7C09169V ADVANCED INFORMATION 3.3V 8K/16K x 9 Synchronous Dual Port Static RAM Features • High-speed clock to data access 10/12 ns max. • 3.3V Low operating power — Active= 135 mA (typical) • True Dual-Ported memory cells which allow simulta­

A12L

Abstract: A13L CY7C09159V CY7C09169V
Contextual Info: 1 CY7C09159V CY7C09169V PRELIMINARY 3.3V 8K/16K x 9 Synchronous Dual Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • Two Flow-Through/Pipelined devices — 8K x 9 organization CY7C09159V

CY7C09159V

Abstract: CY7C09169V
Contextual Info: fax id: 5208 51 CY7C09159V CY7C09169V ADVANCED INFORMATION 3.3V 8K/16K x 9 Synchronous Dual Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 2 Flow-Through/Pipelined devices — 8K x 9 organization CY7C09159V

A12L

Abstract: A13L CY7C09159V CY7C09169V
Contextual Info: fax id: 5208 51 CY7C09159V CY7C09169V PRELIMINARY 3.3V 8K/16K x 9 Synchronous Dual Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 2 Flow-Through/Pipelined devices — 8K x 9 organization CY7C09159V

Contextual Info: fax id: 5208 CY7C09159V CY7C09169V :/ C Y P R E S S 3.3V 8K/16K x 9 Synchronous Dual Port Static RAM • High-speed clock to data access 7.5/12 ns max. • 3.3V Low operating power Features • True Dual-Ported m em ory cells which allow simulta­ neous access of the same memory location

Contextual Info: CYPRESS C Y7C 09159V PRELIMINARY_ C Y 7 C 0 9 1 6 9 V 3.3V 8K/16K x 9 Synchronous Dual Port Static RAM H ig h -s p e ed clo ck to d ata ac c e s s 7.5 l1V9/12 ns m a x. Features 3.3 V Low o p e ratin g p ow er • True D u al-P o rted m e m o ry cells w h ich allo w s im u lta ­

verilog for SRAM 512k word 16bit

Abstract: CY62512V CYM74P436 192-Macrocell 62128 sram 7C1350 Triton P54C palce16v8 programming guide 7C168A intel 16k 8bit RAM chip
Contextual Info: Product Selector Guide Static RAMs Organization/Density Density X1 X4 4K X8 X9 X16 X18 X32 X36 7C148 7C149 7C150 16K 7C167A 7C168A 7C128A 6116 64K to 72K 7C187 7C164 7C166 7C185 6264 7C182 256K to 288K 7C197 7C194 7C195 7C199 7C1399/V 62256/V 62256V25 62256V18