CY7 Search Results

Contextual Info: CY74FCT2541T 8ĆBIT BUFFER/LINE DRIVER WITH 3ĆSTATE OUTPUTS SCCS041B – SEPTEMBER 1994 – REVISED SEPTEMBER 2001 D Function and Pinout Compatible With FCT Q OR SO PACKAGE TOP VIEW and F Logic D 25-Ω Output Series Resistors to Reduce OEA D0 D1 D2 D3

Contextual Info: CY54FCT573T, CY74FCT573T 8-BIT LATCHES WITH 3-STATE OUTPUTS SCCS068 – OCTOBER 2001 D D D D D D D D D D Function and Pinout Compatible With FCT and F Logic Reduced VOH Typically = 3.3 V Versions of Equivalent FCT Functions Edge-Rate Control Circuitry for

Contextual Info: CY74FCT399T QUAD 2-INPUT REGISTER SCCS024A – MARCH 1994 – REVISED OCTOBER 2001 D D D D D D D D Function, Pinout, and Drive Compatible With FCT and F Logic Reduced VOH Typically = 3.3 V Versions of Equivalent FCT Functions Edge-Rate Control Circuitry for

OF946

Contextual Info: CY74FCT16444T/2 H244T Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY74FCT16244T CY74FCT162244T CY74FCT162H244T 16-Bit Buffers/Line Drivers SCCS028B - December 1987 - Revised September 2001

Contextual Info: Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY74FCT16841T CY74FCT162841T 20-Bit Latches SCCS067A - July 1994 - Revised October 2001 Features • • • • • • • • Functional Description

Contextual Info: CY74FCT162H952 T Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY74FCT16952T CY74FCT162952T CY74FCT162H952T 16-Bit Registered Transceivers SCCS065C - August 1994 - Revised September 2001 Features

Contextual Info: CY54FCT244T, CY74FCT244T 8-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCCS071 – OCTOBER 2001 D D D D D D D D OEA DA0 OB0 DA1 OB1 DA2 OB2 DA3 OB3 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC OEB OA0 DB0 OA1 DB1 OA2 DB2 OA3 DB3 CY54FCT244T . . . L PACKAGE

Contextual Info: CY74FCT652T 8-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCCS032B – SEPTEMBER 1994 – REVISED OCTOBER 2001 D D D D D D D D D D Q OR SO PACKAGE TOP VIEW Function, Pinout, and Drive Compatible With FCT and F Logic Reduced VOH (Typically = 3.3 V) Version of

bzx 850

Abstract: bzx 850 30
Contextual Info: CY7C1412AV18 CY7C1414AV18 36 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses

Contextual Info: CY7C1368C 9-Mbit 256 K x 32 Pipelined DCD Sync SRAM 9-Mbit (256 K × 32) Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state

CY7C09449PVA-AC

Abstract: 8c04 i486 PC MOTHERBOARD CIRCUIT diagram
Contextual Info: CY7C09449PVA-AC 128 Kb Dual-Port SRAM with PCI Bus Controller PCI-DP Features Functional Overview • 128 Kb of dual-ported shared memory ■ Master and target PCI Specification 2.2 compliant interface ■ Embedded host bridge capability ■ Direct interface to many microprocessors

Contextual Info: CY7C1346H 2-Mbit 64K x 36 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 36 common I/O architecture • 3.3V core power supply • 3.3V/2.5V I/O operation • Fast clock-to-output times

CY7C1059DV33

Abstract: CY7C1059DV33-10BAXI CY7C1059DV33-10ZSXI
Contextual Info: PRELIMINARY CY7C1059DV33 8-Mbit 1M x 8 Static RAM Functional Description[1] Features • High speed — tAA = 10 ns The CY7C1059DV33 is a high-performance CMOS Static RAM organized as 1M words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an

CY74FCT2573CTQCT

Abstract: CY74FCT2573T CY74FCT573T A115-A C101
Contextual Info: CY74FCT2573T 8-BIT LATCH WITH 3-STATE OUTPUTS SCCS075 – OCTOBER 2001 D D D D D D D D D D Q OR SO PACKAGE TOP VIEW Function and Pinout Compatible With the Fastest Bipolar Logic 25-Ω Output Series Resistors Reduce Transmission-Line Reflection Noise Reduced VOH (Typically = 3.3 V) Version of

Cypress VMEbus Interface Handbook

Abstract: Cypress Applications Handbook 64 pin CERAMIC QUAD FLATPACK 64-pin CERAMIC QUAD FLATPACK CY7C964-ASC G68 Package CY7C960 CY7C961 CY7C964 VIC068A
Contextual Info: 64 CY7C964 Bus Interface Logic Circuit Features • Comparators, counters, latches, and drivers minimize logic requirements for a variety of multiplexed and non-multiplexed buses • Directly drives VMEbus address and data signals • 8-bit comparator for slave address decoding

cypress flash 370

Abstract: logic block diagram of cypress flash 370 device 22v10 CY7C375 FLASH370 o112i cypress flash 370 CPLD cypress flash 370 device technology
Contextual Info: fax id: 6130 For new designs see CY7C375i CY7C375 UltraLogic 128-Macrocell Flash CPLD Features Functional Description • 28 macrocells in eight logic blocks • 28 I/O pins • 6 dedicated inputs including 4 clock pins • Bus Hold capabilities on all I/Os and dedicated inputs

CY7C187

Abstract: CY7C187A
Contextual Info: CY7C187A 64K x 1 Static RAM Features provided by an active LOW chip enable CE and three-state drivers. The CY7C187A has an automatic power-down feature, reducing the power consumption by 55% when deselected. • High speed — 20 ns • CMOS for optimum speed/power

C2665

Abstract: C2668 7c26 C2662 C266 27C64 CY7C266 R1250 C2666
Contextual Info: 1CY 7C26 6 CY7C266 8Kx8 Power-Switched and Reprogrammable PROM Features Functional Description • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military) • Low power — 660 mW (commercial)

CY7C161

Abstract: CY7C162 C1624
Contextual Info: CY7C161 CY7C162 16K x 4 Static RAM with Separate I/O Features Easy memory expansion is provided by active LOW chip enables CE1, CE2 and three-state drivers. They have an automatic power-down feature, reducing the power consumption by 65% when deselected.

7C344-25

Abstract: C344 74HC CY7C344 Signal Path Designer C3445
Contextual Info: CY7C344 32-Macrocell MAX EPLD Features tional I/O pins communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an input, two expanders are used to create an input path. Even if all of the

CY7C1339

Contextual Info: fax id: 1109 PRELIMINARY CY7C1339 128K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 mW standby power (f=0, L version) The CY7C1339 is a 3.3V 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary

C1507

Abstract: C1504 C1502 c1509 C150 CY7C150 R1329
Contextual Info: CY7C150 1Kx4 Static RAM Features Separate I/O paths eliminates the need to multiplex data in and data out, providing for simpler board layout and faster system performance. Outputs are three-stated during write, reset, deselect, or when output enable OE is held HIGH, allowing for

CY7C1022

Contextual Info: Y7C10 PRELIMINARY CY7C1022 32K x 16 Static RAM Features • 5.0V operation ± 10% • High speed — tAA = 12 ns • Low active power — 825 mW (max., 10 ns, “L” version) • Very Low standby power — 500 µW (max., “L” version) • Automatic power-down when deselected

C401 diode

Abstract: 10DC IR transistor 10dc ir C4016 C4019 C401 CY7C401 CY7C402 CY7C403 C4013
Contextual Info: CY7C401/CY7C403 CY7C402/CY7C404 64 x 4 Cascadable FIFO 64 x 5 Cascadable FIFO Features words. Both the CY7C403 and CY7C404 have an output enable OE function. • 64 x 4 (CY7C401 and CY7C403) 64 x 5 (CY7C402 and CY7C404) High-speed first-in first-out memory (FIFO)