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    CQ MET T5 Search Results

    CQ MET T5 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    1P 2F MARKING

    Contextual Info: ADVANCE |v i i c 2 5 6 K x 1 8 /1 2 8 K x 36 3 . 3 V Vod, HSTL. PIPELINED C L A Y M O R E SRAM :r o n R M h tt. U I V I U M T57L256H 18P M T57L128H 36P d FEATURES • • • • • • • • • • • • • • • • • • • • • Fast cycle times: 4.4ns, 5ns, 5.5ns, 6ns and 7ns


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    T57L256H T57L128H 18/126K MT57L256H18P C1996, 1P 2F MARKING PDF

    Contextual Info: VME 1210/1220 A 3 L May 1989 Slot 1 and Non-Slot 1 VMEbus Master Controllers Distinctive Features_ • VME 1210 provides two device chip set for slot 1 master bus controller and single level arbiter Applications_


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    pro15-17, PDF

    AG29

    Abstract: ipug45_01.5 transistor w1d transistor w4B SRAM SAMSUNG FC1152 3ah22
    Contextual Info: ispLever CORE TM QDRII+ SRAM Controller MACO Core User’s Guide June 2008 ipug45_01.5 QDRII+ SRAM Controller MACO Core User’s Guide Lattice Semiconductor Introduction Lattice’s QDRII and QDRII+ QDRII/II+ SRAM Controller MACO core assists the FPGA designer’s efforts by


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    ipug45 AG29 ipug45_01.5 transistor w1d transistor w4B SRAM SAMSUNG FC1152 3ah22 PDF

    VME bus controller

    Abstract: PLD VME VME bus arbitration 1210a vme bus specification 1210B vme case 1210 LCC
    Contextual Info: VME 1210/20 Slot 1 and Non-Slot 1 VMEbus Master Controllers March 1989 Distinctive Features. * VME 1210 provides two device chip set for slot 1 master bus controller and single level arbiter * VME 1220 provides two device chip set for non-slot 1 master bus controller


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    PDF

    74ACT563

    Abstract: 74ACT563SC ACT573 MS-013
    Contextual Info: . Revised D ecem ber 1998 S E M IC Ü N D U C T Ü R tm 74ACT563 Octal Latch with 3-STATE Outputs General Description Features T h e AC T563 is a high-speed octal latch w ith buffered com ­ mon Latch Enable LE and buffered com m on Output Enable (OE) inputs.


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    74ACT563 ACT563 ACT573, ACT573 74ACT563 74ACT563SC MS-013 PDF

    Contextual Info: WAY 1 0 JSJ3 VME 1210/1220 June 1990 Slot 1 and Non-Slot 1 VMEbus Master Controllers Distinctive Features_ • VME 1210 provides two device chip set for slot 1 master bus controller and single level arbiter • VME 1220 provides two device chip set for non-slot 1


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    1210/12duct 24-Lead 28-Pin DGD02S2 24-Pin 10TYP PDF

    VME DAISY CHAIN

    Contextual Info: VME 1210/20 Slot 1 and Non-Slot 1 VMEbus Master Controllers March 1989 Applications-* VMEbus masters residing in slot 1 boards VME 1210 * VMEbus masters residing in non-slot 1 boards (VME 1220) Distinctive Features_


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    1210B VME DAISY CHAIN PDF

    2p 2t

    Abstract: 8p p
    Contextual Info: ADVANCE 25 6 K x 1 8 / 1 2 8K x 36 2. 5V V dd , H S T L , P I P E L I N E D C L A Y M O R E S R A M MICRON TECHNOLOGY, INC. U MT57V256H18P MT57V128H36P 4.5Mb C L A Y M O R E SRAM FEATURES Fast cycle times: 4.4ns, 5ns, 5.5ns, 6ns and 7ns * 256K x 18 and 128K x 36 configurations


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    PDF

    Contextual Info: ADVANCE 256K X 18/128K x 36 2.5V V dd, HSTL, PIPELINED CLAYMORE SRAM MICRON I TECHNOLOGY, INC. MT57V256H18P MT57V128H36P 4.5Mb CLAYMORE SRAM FEATURES • • • • • • • • • • • • • • • • • • • • • Fast cycle times: 4.4ns, 5ns, 5.5ns, 6ns and 7ns


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    18/128K MT57V256H18P MT57V128H36P PDF

    Contextual Info: E NM XXS' ATA06212D1C AGC Transimpedance Amplifier SONET OC-12 Preliminary Your GaAs IC Source REV 0 FEATURES APPLICATIONS • Single +5 Volt Supply ■ SONET OC-12/SDH STM-4 Receiver ■ Automatic Gain Control ■ Excellent Sensitivity - 34 dBm ■ Low Noise RF Amplifier


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    ATA06212D1C OC-12 OC-12/SDH ATA062J2 ATA06212 PDF

    t54 sot-23

    Abstract: 7s00 NC7S00 4011 CMOS NAND GATE MA05B NC7S00M5
    Contextual Info: ß February 1996 NC7S00 Tiny 2-Input NAND Gate General Description Features The NC7S00 is a single 2-Input high performance CMOS NAND Gate in National’s TinyPak package. Advanced Silicon Gate CMOS fabrication assures high speed and low power circuit operation over a broad V ex range. ESD pro­


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    NC7S00 NC7S00 t54 sot-23 7s00 4011 CMOS NAND GATE MA05B NC7S00M5 PDF

    Contextual Info: Semiconductor General Description G uaranteed sim ultaneous sw itching noise level and dynam ic threshold perform ance The ’A C Q /’AC TQ 573 is a high-speed octal latch with buff­ ered com m on Latch Enable LE and buffered com m on O ut­ put Enable (OE) inputs. The ’A C Q /’AC TQ 573 is functionally


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    54ACQ573 54ACTQ573 itch0-272-9959 PDF

    Contextual Info: E2G0131-17-61 O K I Semiconductor MSM51V18160D/DSL 1,048,576-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM51V18160D/DSL is a 1,048,576-word x 16-bit dynamic RAM fabricated in Oki's silicongate CMOS technology. The MSM51V18160D / DSL achieves high integration, high-speed operation,


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    E2G0131-17-61 MSM51V18160D/DSL 576-Word 16-Bit MSM51V18160D/DSL MSM51V18160D 42-pin PDF

    TMS626812

    Contextual Info: TMS626812 1048576-WORD BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY _ SMOS687A -JULY 1 9 9 6- REVISED APRIL 1997 • • • Organization . . . 1M x 8 x 2 Banks 3.3-V Power Supply ± 10% Tolerance Two Banks for On-Chip Interleaving


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    TMS626812 1048576-WORD SMOS687A 83-MHz PDF

    573SJ

    Contextual Info: S E M IC O N D U C T O R January 1990 Revised D ecem ber 1998 TM 74ACQ573 74ACTQ573 Quiet Series Octal Latch with 3-STATE Outputs General Description Features T h e AC Q/AC TQ 573 is a high-speed octal latch with buff­ ered com m on Latch Enable LE and buffered com m on


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    74ACQ573 74ACTQ573 573SJ PDF

    L1349

    Contextual Info: PRELIMINARY DATA SHEET N EC MOS INTEGRATED CIRCUIT MC-424000LAB72F 3.3 V OPERATION 4M -WORD BY 72-BIT DYNAMIC RAM MODULE FAST PAGE MODE ECC Description The MC-424000LAB72F is a 4 194 304 words by 72 bits dynamic RAM module on which 18 pieces of 16M DRAM ( m PD 4217400L) are assembled.


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    MC-424000LAB72F 72-BIT MC-424000LAB72F 4217400L) 424000LAB72-60 424000LAB72-70 110ns 130ns bM57S25 L1349 PDF

    gigabyte 945

    Abstract: architecture diagram for 8080 e600 MPC740 MPC7450 MPC750 SR15 E600COREPB SPR284 physical counter multiprocessor out-of-order
    Contextual Info: Freescale Semiconductor Product Brief E600COREPB Rev. 0, 11/2004 e600 Core Product Brief This product brief provides an overview of the e600 core features, including a block diagram showing the major functional components. The e600 is a PowerPC core. This document also provides information about how the e600 implementation complies with the PowerPC and


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    E600COREPB 32-Kbyte gigabyte 945 architecture diagram for 8080 e600 MPC740 MPC7450 MPC750 SR15 E600COREPB SPR284 physical counter multiprocessor out-of-order PDF

    MPC740

    Abstract: MPC7441 MPC7445 MPC7450 MPC7451 MPC7455 MPC750 SR15
    Contextual Info: Advance Information MPC7450TS/D Rev. 2, 01/2002 MPC7450 RISC Microprocessor Family Technical Summary This technical summary provides an overview of the MPC7451 microprocessor features, including a block diagram showing the major functional components. It also provides


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    MPC7450TS/D MPC7450 MPC7451 MPC7441, MPC7445, MPC7455. MPC7450, MPC740 MPC7441 MPC7445 MPC7455 MPC750 SR15 PDF

    Contextual Info: HIP6006 Semiconductor Buck and Synchronous-Rectifier Pulse-Width Modulator PWM Controller September 1997 Features Description • Drives Two N-Channel MOSFETs The HIP6006 provides complete control and protection for a DC-DC converter optimized for high-performance micropro­


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    HIP6006 HIP6006 AN9722. 680nF T50-52B; 17AWG N4148 MBR340 RFP25N05 PDF

    do9-15

    Abstract: TOT - 4301 do9-1 4880M D08-15 CH371 HY51V4264B
    Contextual Info: HYUNDAI HY51V4264B Series 256Kx 16-bit CMOS DRAM with Extended Data Out PRELIMINARY DESCRIPTION The HY51V4264B is the new generation and fast dynamic RAM organized 262,144 x 16-bit configuration employing advance submicron CMOS process technology and advanced circuit design technique to achieve fast


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    HY51V4264B 16-bit HV51V4264B 400mil 40pin 40/44pin Q0D43G3 1AC30-10-MAY95 do9-15 TOT - 4301 do9-1 4880M D08-15 CH371 PDF

    Hitachi DSA007579

    Abstract: HM5117400AS HB56A841BR-6A Hitachi DSA00757 Hitachi DSA0075
    Contextual Info: HB56A841BR Series 8,388,608-Word x 40-Bit High Density Dynamic RAM Module Rev. 1 Mar. 01, 1994 The HB56A841BR is a 8 M x 40 dynamic RAM module, mounted 20 pieces of 16-Mbit DRAM HM5117400AS sealed in SOJ package. An outline of the HB56A841BR is 72-pin single in-line


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    HB56A841BR 608-Word 40-Bit 16-Mbit HM5117400AS) 72-pin Hitachi DSA007579 HM5117400AS HB56A841BR-6A Hitachi DSA00757 Hitachi DSA0075 PDF

    Contextual Info: IMICRON TCCHWLOOY.INC. S MT48LC1M16A1 S - 512K SYNCHRONOUS DRAM V dd DQ0 DQ1 VssQ DQ2 DQ3 V ddQ DQ4 DQ5 VssQ DQ6 DQ7 V ddQ DQML W E# CAS# RAS# CS# BA A10 A0 A1 A2 A3 V dd M ARKING N ote: 1 M eg x 16 1• 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21


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    048-cycle 096-cycle 50-PIN 16MSDRAMx16 PDF

    Contextual Info: SIEMENS 16M X 4-Bit Dynamic RAM 4k & 8k-Refresh HYB 3164400AJ/AT(L) -40/-50/-60 HYß 3165400AJ/AT(L) -40/-50/-60 Prelim inary Inform ation • 16 777 216 words by 4-bit organization • 0 to 70 °C operating temperature • Fast Page M ode operation •


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    3164400AJ/AT 3165400AJ/AT 400AJ/AT PDF

    TN-58-11

    Abstract: 18B-3
    Contextual Info: |V |IC =R O N 64K SYNCHRONOUS SRAM M T5 8LC 64K 16/18B3 16/18 SY N C B U R S T SRAM X 64Kx 16/18 SRAM FEATURES • • • • • • • • • • • • • • • • Fast access times: 8.5, 9,10 and 11ns Fast OE# access time: 5ns Single +3.3V +10%/-5% pow er supply


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    16/18B3 100-lead MT58LC64K16/13B3 TN-58-11 18B-3 PDF