CQ 1265 Search Results

CQ 1265

Contextual Info: GS81302Q08/09/18/36E-333/300/250 333 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 144Mb SigmaQuadTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

Contextual Info: GS81302Q08/09/18/36E-333/300/250 333 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 144Mb SigmaQuadTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features Clocking and Addressing Schemes • Simultaneous Read and Write SigmaQuad Interface

Contextual Info: GS81302Q08/09/18/36E-333/300/250 144Mb SigmaQuadTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

Contextual Info: CY7C1310V18 CY7C1312V18 CY7C1314V18 PRELIMINARY 18-Mb QDR -II SRAM 2-Word Burst Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth • 2-Word Burst on all accesses

CQ 1265

Abstract: 3M Touch Systems
Contextual Info: CY7C1261KV18, CY7C1276KV18 CY7C1263KV18, CY7C1265KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports

Contextual Info: CY7C12611KV18, CY7C12761KV18 CY7C12631KV18, CY7C12651KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Functional Description • Separate independent read and write data ports

3M Touch Systems

Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-53193 Spec Title: CY7C12611KV18/CY7C12761KV18/CY7C12631KV18/ CY7C12651KV18, 36-MBIT QDR R II+ SRAM 4-WORD BURST ARCHITECTURE (2.5 CYCLE READ LATENCY) Sunset Owner: Robert Cajustin (AJU) Replaced by: None CY7C12611KV18, CY7C12761KV18

3M Touch Systems

Contextual Info: CY7C1261KV18, CY7C1276KV18 CY7C1263KV18, CY7C1265KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports

Contextual Info: CY7C1261KV18, CY7C1276KV18 CY7C1263KV18, CY7C1265KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports

Contextual Info: CY7C1263KV18/CY7C1265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions

3M Touch Systems

Contextual Info: CY7C1263KV18, CY7C1265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions

Contextual Info: GS81302Q07/10/19/37E-318/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface

Contextual Info: GS81302Q07/10/19/37E-318/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface

GS81302Q37GE-333

Contextual Info: GS81302Q07/10/19/37E-333/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–200 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

d33 02C

Contextual Info: GS81302Q07/10/19/37E-318/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface

Contextual Info: CY7C1263XV18/CY7C1265XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate Independent Read and Write Data Ports

Contextual Info: GS81302QT07/10/19/37E-318/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface

CQ 1265

Abstract: AN1021
Contextual Info: GS81302QT07/10/19/37E-333/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface

3M Touch Systems

Contextual Info: CY7C1263XV18, CY7C1265XV18 36-Mbit QDR II+ Xtreme SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ Xtreme SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate Independent Read and Write Data Ports

GS81302QT19GE-200

Contextual Info: GS81302QT07/10/19/37E-333/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–200 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

GS81302QT07E-300

Contextual Info: GS81302QT07/10/19/37E-318/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface

Contextual Info: CY7C1263XV18, CY7C1265XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Configurations Features Separate Independent Read and Write Data Ports

3M Touch Systems

Contextual Info: CY7C1263XV18, CY7C1265XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate Independent Read and Write Data Ports

Contextual Info: 10 NO TES: 1. HOUSING M A T E R IA L : LC P , G L A S S F IL L E D , U L 9 4 V - 0 COLOUR B L A C K . - .0 4 4 1 .0 0 3 (1.12 ± 0.08 .0 7 9 2 . 00 ) 2. T E R M IN A L M A T E R IA L : P H O S P H O R BR O N ZE 3 . S E E A P P R O P R IA T E S H E E T FO R CIRCUIT S IZE ,