CQ 1265 Search Results
CQ 1265 Result Highlights (5)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
|---|---|---|---|---|---|
| 88951-265LF |
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Metral® Board Connectors, Backplane Connectors, 4 Row Signal Header, Straight, Solder-to-Board, Wide body. | |||
| GSB12651AEU |
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USB 2.0 Type A, Receptacle, Right Angle Sink, 4.3mm Height, 4 Pins, Shell with Matte Plating, 15u\\ Gold, Dip 2.5mm, Shell Forklock, Black High Temperature Housing, Tape and Reel Packaging | |||
| 61126-502CALF |
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Assembly, Bottom Mount, S/D(68Pins),SMT I.L., Type 123, 3.3V, 0mm s/o, Right Push Rod Eject, 8mm Card Travel, Narrow Body | |||
| 88921-265LF |
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4 Row Signal Header, Straight, Press-Fit, 1 Mod | |||
| 10153126-5T2LF |
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1.8MM WIRE TO BOARD RECEPTACLE |
CQ 1265 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
CQ 1265Contextual Info: GS81302Q08/09/18/36E-333/300/250 333 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 144Mb SigmaQuadTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package |
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gs81302q08/09/18/36e-333/300/250165-bump144mb81302qxx+1 | |
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Contextual Info: GS81302Q08/09/18/36E-333/300/250 333 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 144Mb SigmaQuadTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features Clocking and Addressing Schemes • Simultaneous Read and Write SigmaQuad Interface |
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gs81302q08/09/18/36e-333/300/250165-bump144mb81302qxx | |
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Contextual Info: GS81302Q08/09/18/36E-333/300/250 144Mb SigmaQuadTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package |
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gs81302q08/09/18/36e-333/300/250165-bump144mb81302qxx | |
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Contextual Info: CY7C1310V18 CY7C1312V18 CY7C1314V18 PRELIMINARY 18-Mb QDR -II SRAM 2-Word Burst Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth • 2-Word Burst on all accesses |
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cy7c1310v18cy7c1312v18cy7c1314v1818-mb+2 | |
CQ 1265
Abstract: 3M Touch Systems
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Original |
36-mbitcy7c1261kv18cy7c1276kv18cy7c1263kv18+3 | |
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Contextual Info: CY7C12611KV18, CY7C12761KV18 CY7C12631KV18, CY7C12651KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Functional Description • Separate independent read and write data ports |
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cy7c12611kv18cy7c12761kv18cy7c12631kv18cy7c12651kv18+1 | |
3M Touch SystemsContextual Info: THIS SPEC IS OBSOLETE Spec No: 001-53193 Spec Title: CY7C12611KV18/CY7C12761KV18/CY7C12631KV18/ CY7C12651KV18, 36-MBIT QDR R II+ SRAM 4-WORD BURST ARCHITECTURE (2.5 CYCLE READ LATENCY) Sunset Owner: Robert Cajustin (AJU) Replaced by: None CY7C12611KV18, CY7C12761KV18 |
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y7c12611kv18/cy7c12761kv18/cy7c12631kv18/cy7c12651kv1836-mbitcy7c12611kv18+3 | |
3M Touch SystemsContextual Info: CY7C1261KV18, CY7C1276KV18 CY7C1263KV18, CY7C1265KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports |
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36-mbitcy7c1261kv18cy7c1276kv18cy7c1263kv18+2 | |
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Contextual Info: CY7C1261KV18, CY7C1276KV18 CY7C1263KV18, CY7C1265KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports |
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cy7c1261kv18cy7c1276kv18cy7c1263kv18cy7c1265kv18+1 | |
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Contextual Info: CY7C1263KV18/CY7C1265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions |
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cy7c1263kv18/cy7c1265kv1836-mbitcy7c1265kv18 | |
3M Touch SystemsContextual Info: CY7C1263KV18, CY7C1265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions |
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cy7c1263kv18cy7c1265kv1836-mbit3m touch systems | |
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Contextual Info: GS81302Q07/10/19/37E-318/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface |
Original |
gs81302q07/10/19/37e-318/300/250/200165-bump81302q1937 | |
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Contextual Info: GS81302Q07/10/19/37E-318/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface |
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gs81302q07/10/19/37e-318/300/250/200144mb165-bump81302q1937 | |
GS81302Q37GE-333Contextual Info: GS81302Q07/10/19/37E-333/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–200 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package |
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gs81302q07/10/19/37e-333/300/250/200165-bump81302q1937gs81302q37ge-333 | |
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d33 02CContextual Info: GS81302Q07/10/19/37E-318/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface |
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gs81302q07/10/19/37e-318/300/250/200165-bumpavai0/250/20081302q1937+1 | |
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Contextual Info: CY7C1263XV18/CY7C1265XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate Independent Read and Write Data Ports |
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cy7c1263xv18/cy7c1265xv1836-mbitcy7c1265xv18 | |
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Contextual Info: GS81302QT07/10/19/37E-318/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface |
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gs81302qt07/10/19/37e-318/300/250/200144mb165-bump81302qt1937e | |
CQ 1265
Abstract: AN1021
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Original |
gs81302qt07/10/19/37e-333/300/250/200144mb165-bumpgs81302qtxxe-300t+3 | |
3M Touch SystemsContextual Info: CY7C1263XV18, CY7C1265XV18 36-Mbit QDR II+ Xtreme SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ Xtreme SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate Independent Read and Write Data Ports |
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36-mbitcy7c1263xv18cy7c1265xv183m touch systems | |
GS81302QT19GE-200Contextual Info: GS81302QT07/10/19/37E-333/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–200 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package |
Original |
gs81302qt07/10/19/37e-333/300/250/200165-bumpgs81302qtxxe-300t81302qt1937e+1 | |
GS81302QT07E-300Contextual Info: GS81302QT07/10/19/37E-318/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface |
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gs81302qt07/10/19/37e-318/300/250/200165-bump81302qt1937egs81302qt07e-300 | |
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Contextual Info: CY7C1263XV18, CY7C1265XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Configurations Features Separate Independent Read and Write Data Ports |
Original |
cy7c1263xv18cy7c1265xv1836-mbit | |
3M Touch SystemsContextual Info: CY7C1263XV18, CY7C1265XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate Independent Read and Write Data Ports |
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cy7c1263xv18cy7c1265xv1836-mbit3m touch systems | |
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Contextual Info: 10 NO TES: 1. HOUSING M A T E R IA L : LC P , G L A S S F IL L E D , U L 9 4 V - 0 COLOUR B L A C K . - .0 4 4 1 .0 0 3 (1.12 ± 0.08 .0 7 9 2 . 00 ) 2. T E R M IN A L M A T E R IA L : P H O S P H O R BR O N ZE 3 . S E E A P P R O P R IA T E S H E E T FO R CIRCUIT S IZE , |
OCR Scan |
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