CQ 106 Search Results

IS61QDB22M36

Abstract: D0-35 IS61QDB24M18
Contextual Info: 72 Mb 2M x 36 & 4M x 18 QUAD (Burst of 2) Synchronous SRAMs . A May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Two echo clocks (CQ and CQ) that are delivered

Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT PD44165082A, 44165092A, 44165182A, 44165362A 18M-BIT QDRTMII SRAM 2-WORD BURST OPERATION Description The μPD44165082A is a 2,097,152-word by 8-bit, the μPD44165092A is a 2,097,152-word by 9-bit, the μPD44165182A is a 1,048,576-word by 18-bit and the μPD44165362A is a 524,288-word by 36-bit synchronous quad data rate static RAM

10D-11

Abstract: K7R160982B K7R160982B-FC16 K7R160982B-FC20 K7R161882B K7R161882B-FC16 K7R161882B-FC20 K7R163682B K7R163682B-FC16 K7R163682B-FC20
Contextual Info: K7R163682B K7R161882B K7R160982B 512Kx36 & 1Mx18 & 2Mx9 QDR TM II b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit, 2Mx9-bit QDRTM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Oct. 17, 2002 Advance 0.1 1. Change the Boundary scan exit order.

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT PD44324084, 44324094, 44324184, 44324364 36M-BIT DDR II SRAM 4-WORD BURST OPERATION Description The μPD44324084 is a 4,194,304-word by 8-bit, the μPD44324094 is a 4,194,304-word by 9-bit, the μPD44324184 is a 2,097,152-word by 18-bit and the μPD44324364 is a 1,048,576-word by 36-bit synchronous double data rate static RAM

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT PD44164082A, 44164092A, 44164182A, 44164362A 18M-BIT DDRII SRAM 2-WORD BURST OPERATION Description The μPD44164082A is a 2,097,152-word by 8-bit, the μPD44164092A is a 2,097,152-word by 9-bit, the μPD44164182A is a 1,048,576-word by 18-bit and the μPD44164362A is a 524,288-word by 36-bit synchronous double data rate static

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT PD44324082, 44324092, 44324182, 44324362 36M-BIT DDR II SRAM 2-WORD BURST OPERATION Description The μPD44324082 is a 4,194,304-word by 8-bit, the μPD44324092 is a 4,194,304-word by 9-bit, the μPD44324182 is a 2,097,152-word by 18-bit and the μPD44324362 is a 1,048,576-word by 36-bit synchronous double data rate static RAM

D0-35

Abstract: K7J161882B K7J161882B-FC16 K7J161882B-FC20 K7J161882B-FC25 K7J163682B K7J163682B-FC16 K7J163682B-FC20 K7J163682B-FC25
Contextual Info: K7J163682B K7J161882B 512Kx36 & 1Mx18 DDR II SIO b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Dec. 16, 2002 Advance 0.1 1. Change the JTAG Block diagram Dec. 26, 2002 Preliminary

D0-35

Abstract: K7J321882M K7J321882M-FC16 K7J321882M-FC20 K7J321882M-FC25 K7J323682M K7J323682M-FC16 K7J323682M-FC20 K7J323682M-FC25
Contextual Info: K7J323682M K7J321882M 1Mx36 & 2Mx18 DDR II SIO b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. July, 15 200 1 Advance 0.1 1. 2. 3. 4. 5. 6. Dec, 14 2001 Preliminary 0.2 1. Update current characteristics in DC electrical characteristics

Contextual Info: 72 Mb 2M x 36 & 4M x 18 QUAD (Burst of 2) Synchronous SRAMs . Advanced Information January 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations.

HM66AQB18204

Abstract: HM66AQB36104 HM66AQB36104BP-30 HM66AQB36104BP-33 HM66AQB36104BP-40 HM66AQB9404 of 8404
Contextual Info: To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

MT57W2MH8B

Abstract: MT57W512H36B MT57W1MH18B
Contextual Info: 2 MEG X 8, 1 MEG X 18, 512K X 36 1.8V VDD, HSTL, DDRIIb2 SRAM 18Mb DDRII CIO SRAM 2-Word Burst MT57W2MH8B MT57W1MH18B MT57W512H36B Features • • • • • • • • • • • • • • • • • DLL circuitry for accurate output data placement

D0-35

Abstract: IS61QDB42M36 IS61QDB42M36-300M3 IS61QDB44M18 IS61QDB44M18-300M3
Contextual Info: 72 Mb 2M x 36 & 4M x 18 QUAD (Burst of 4) Synchronous SRAMs 7 Q . May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with late write operation.

Contextual Info: 72 Mb 2M x 36 & 4M x 18 QUADP (Burst of 4) Synchronous SRAMs 7 Q . I Advanced Information May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations.

Contextual Info: PRELIMINARY‡ 2 MEG X 8, 1 MEG X 18, 512K X 36 1.8V VDD, HSTL, DDRIIb4 SRAM 18Mb DDRII CIO SRAM 4-WORD BURST MT57W2MH8J MT57W1MH18J MT57W512H36J Features • • • • • • • • • • • • • • • • DLL circuitry for accurate output data placement

Contextual Info: PRELIMINARY‡ 2 MEG X 8, 1 MEG X 18, 512K X 36 1.8V VDD, HSTL, DDRIIb2 SRAM 18Mb DDRII CIO SRAM 2-Word Burst MT57W2MH8B MT57W1MH18B MT57W512H36B Features • • • • • • • • • • • • • • • • • DLL circuitry for accurate output data placement

Contextual Info: ADVANCE‡ 4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, DDRIIb2 SRAM 36Mb DDRII CIO SRAM 2-WORD BURST MT57W4MH8B MT57W4MH9B MT57W2MH18B MT57W1MH36B Features • • • • • • • • • • • • • • • • • Figure 1: 165-Ball FBGA

Contextual Info: IS61QDP2B42M18A/A1/A2 IS61QDP2B41M36A/A1/A2 2Mx18, 1Mx36 36Mb QUADP Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                     1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data

Contextual Info: Datasheet R1QGA4436RBG,R1QGA4418RBG 144-Mbit QDR II+ SRAM 4-word Burst Architecture 2.0 Cycle Read latency R10DS0139EJ0200 Rev.2.00 Jun 01, 2013 Description The R1QGA4436RBG is a 4,194,304-word by 36-bit and the R1QGA4418RBG is a 8,388,608-word by 18-bit

Contextual Info: ISSI IS61LSSD102418 ΣQUAD 18Mb Σ2x2B4 ADVANCE INFORMATION DECEMBER 2002 DDR SEPARATE I/O SRAM FEATURES • Simultaneous Read and Write SigmaQuad Interface • JEDEC standard pinout and package • Dual Double Data Rate interface • Echo Clock outputs track data output drivers

Contextual Info: K7I323684M K7I321884M K7I320884M Preliminary 1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDRII CIO b4 SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. October, 22 2001 Advance 0.1 1. Pin name change from DLL to Doff.

Contextual Info: IS61QDP2B44M18A/A1/A2 IS61QDP2B42M36A/A1/A2 4Mx18, 2Mx36 72Mb QUADP Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES • • • • • • • • • • • • • • • • • • • • • 2Mx36 and 4Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data

K7R161884B

Abstract: K7R161884B-FC25 K7R161884B-FC30 K7R163684B K7R163684B-FC16 K7R163684B-FC20 K7R163684B-FC25 K7R163684B-FC30
Contextual Info: K7R163684B K7R161884B K7R160884B Preliminary 512Kx36 & 1Mx18 & 2Mx8 QDR TM II b4 SRAM Document Title 512Kx36-bit,1Mx18-bit, 2Mx8-bit QDR TM II b4 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Oct. 17. 2002 Advance 0.1 1. Change the Boundary scan exit order.

IS61DDB21M36

Abstract: 61DDB22M18 IS61DDB22M18-300M3L IS61DDB22M18 IS61DDB22M18-250M3LI
Contextual Info: 36 Mb 1M x 36 & 2M x 18 DDR-II (Burst of 2) CIO Synchronous SRAMs . I May 2009 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late