COREWARE LIBRARY Search Results

PQ-32/AMS-DTL-23053/4 ATUM

Abstract: pid u 13t lsi r3000 LSI coreware library CW4001
Contextual Info: LSI LOGIC Description MiniRISC MR4001 Microprocessor Lead Vehicle Preliminary Datasheet The MiniRISC MR4001 Microprocessor Lead Vehicle is a chip implementation of the MiniRISC CW4001 Microprocessor, a component of LSI Logic’s CoreWare Library. The

TAG 8822

Abstract: tag 9327 maa 502 CWDSP1650 0x0000-0xFDFF C15018 LSI coreware library
Contextual Info: CWDSP1650 OakDSPCore Preliminary Datasheet Description The CWDSP1650 OakDSPCore, a component of the LSI Logic CoreWare Library, is a 16-bit, high-performance, fixed-point Digital Signal Processing DSP core for midrange to high-end telecommunications and consumer electronics applications. The core provides a

MR4010

Abstract: STR MR4010 SW-SPDT-mom MR4010 circuit HC 5287 LDP16 J132 regulator BDMR4010 2 pin dip switch str 2105
Contextual Info: MiniRISC BDMR4010 Evaluation Board User’s Guide A CoreWare Product Preliminary Order Number C14035 This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the

coreware graphics

Abstract: verilog code for superscalar mips
Contextual Info: LSI LOGIC Description MiniRISC CW4010 Superscalar Microprocessor Core Preliminary D atash eet LSI Logic Corporation has developed the MiniRISC CW4010 Superscalar Microprocessor Core, the world’s first MIPS-ll-compatible superscalar core, using LSI Logic’s CoreWare

CW4001

Contextual Info: LSI LOGIC CWDSP1650 OakDSPCore Prelim inary Datasheet Description The CW DSP1650 OakDSPCore, a component of the LSI Logic CoreWare Library, is a 16-bit, high-performance, fixed-point Digital Signal Processing DSP) core for midrange to high-end telecommunications and consumer electronics applications. The core provides a

ccu g11

Abstract: CWDSP1650 CWDSP1670 "vector instructions" saturation arithmetic left shift
Contextual Info: CWDSP1670 DSP Core Preliminary Datasheet The CWDSP1670 DSP Core, a component of the LSI Logic CoreWare Library, is a 16-bit, high-performance, fixed-point Digital Signal Processing DSP core for mid- to high-end telecommunications and consumer electronics applications. It is a low-cost, high-performance

LSI 1394a

Abstract: pht 094 IEC61883 LSI Logic ASIC
Contextual Info: 1394 Node Controller Core IEEE 1394a Node Controller Core Features Overview The 1394 Node Controller Core is a member of the LSI Logic CoreWare family of design building blocks. The 1394 Node Controller Core macro, when combined with a CPU processor and PHY core, provides a fully functional integrated

LSI 1394a

Abstract: LSI LOGIC pht 094 IEC61883
Contextual Info: 1394 Node Controller Core IEEE 1394a Node Controller Core Features Overview The 1394 Node Controller Core is a member of the LSI Logic CoreWare family of design building blocks. The 1394 Node Controller Core macro, when combined with a CPU processor and PHY core, provides a fully functional integrated

oak dsp

Abstract: "vector instructions" saturation
Contextual Info: LSI LOGIC Description CWDSP1640 Oak DSP Core Datasheet The CWDSP1640 Oak DSP Core, a component of the LSI Logic CoreWare Library, is a 16-bit, high-performance, fixed-point Digital Signal Processing DSP core designed for mid­ dle to high-end telecommunications applications and consumer electronics. The core pro­

LR33300

Abstract: yx 801 cw33300 LSI CoreWare CW33300 Enhanced Self-Embedding Processor Core tag 8638 Rato* RT 1072 DI-22 DI-31 LR3330
Contextual Info: MiniRISC CW4011 Superscalar Microprocessor Core Technical Manual A CoreWare® Product ® Order Number C14040.A Document DB14-000064-01, Second Edition May 1999 This document describes revision A of LSI Logic Corporation’s MiniRISC® CW4011 Superscalar Microprocessor Core and will remain the official reference

Contextual Info: CW001007 ARM7TDMI Microprocessor Core Datasheet The LSI Logic CW001007 core is an implementation of the Advanced RISC Machines ARM7TDMI 32-bit RISC microprocessor developed by Advanced RISC Machines. The CW1007 meets the requirements of the LSI Logic CoreWare methodology and is implemented using LSI Logic

modified harvard architecture

Abstract: 3955K oak dsp CWDSP1640
Contextual Info: CWDSP1640 Oak DSP Core Datasheet Description The CWDSP1640 Oak DSP Core, a component of the LSI Logic CoreWare Library, is a 16-bit, high-performance, fixed-point Digital Signal Processing DSP core designed for middle to high-end telecommunications applications and consumer electronics. The core provides a low-cost, high-performance solution for applications that require low power and

pal 007c

Abstract: b1100 nec LDP16 sulzer s7 7-segment countdown timer MDP36 100LQ128 3pin round shell connector DP83932B LT1084CT-3.3
Contextual Info: MiniRISC BDMR4011 Evaluation Board User’s Guide A CoreWare® Product March 1998 ® Order Number XXXXX Document DB15-000055-00, First Edition March 1998 This document describes revision A of LSI Logic Corporation’s BDMR4011 Evaluation Board and will remain the official reference source for all revisions/releases of this product until rescinded by an update.

EZ4021

Contextual Info: EZ4021 MiniRISC EasyMACRO TM Integrated MiniRISC ® MIPS Microprocessor Core Overview The EZ4021 extends the LSI Logic MIPS MiniRISC® family with a high performance 64-bit microprocessor. The EZ4021 EasyMACRO is an optimized implementation of a synthesizeable core that operates up to 250MHz under worst

LSI coreware library

Abstract: LSI LOGIC OakDSPCore "Hot Plug and Play"
Contextual Info: USB Host Core Host Core for Universal Serial Bus Solutions Overview The USB Host Core, a component of LSI Logic’s comprehensive USB solution set, is a flexible and configurable core that manages and generates the Universal Serial Bus, providing support of USB peripherals in highly integrated embedded systems.

ARM926EJ-S

Abstract: ARM processor data flow ARM926EJScore embedded trace macrocell ARM926EJ etm lsi logic
Contextual Info: 266/200MHz ARM926EJ-S Cores with Linux and Java Support OVERVIEW FEATURES LSI Logic offers the ARM926EJ-S processor core synthesized onto both our Gflx 0.11 micron drawn and G12P 0.18 micron (drawn) high performance process technologies. • 266MHz Gflx ARM926EJ-S

LSI LOGIC

Abstract: "USB Transceiver" LSI coreware library "Hot Plug and Play"
Contextual Info: USB Function Core Overview LSI Logic’s USB Function Core is a flexible and configurable core interfacing a peripheral function to the Universal Serial Bus and enabling the design of highly integrated peripheral single-chip systems. Combining the USB Function core and LSI Logic’s USB transceiver I/Os with

ARM1156T2-S

Abstract: AMBA AXI to APB BUS Bridge AMBA AXI to APB BUS Bridge architecture PL022 AXI-64 interface ARM processor data flow PL300 AMBA AHB to AXI AMBA AHB bus protocol ARM1156T2S
Contextual Info: ARM1156T2-S TCM-only Processor with ECC Protection and Reference Design CW001145 FEATURES • 450 MHz timing-closed hardmac OVERVIEW The LSI Logic implementation of the ARM1156T2-S processor for cell-based ASIC provides an integration friendly solution for applications like mass storage

MIPS

Abstract: MIPS R4000 EZ4030 R4000 mips r4000 block diagram
Contextual Info: EZ4030 240MHz 64-bit MIPS Processor Core with integrated FPU INTEGRATED MINIRISC® MIPS MICROPROCESSOR CORE OVERVIEW The EZ4030 extends the LSI Logic MIPS MiniRISC® family with a high performance 64-bit microprocessor. The EZ4030 EasyMACRO is an optimized

G12-l

Abstract: LSI Logic ASIC g12 High Voltage G12L g12 transistor G12 000
Contextual Info: G12 ASIC Cell-Based Product Features/ Benefits Twelfth Generation ASIC Technology • ASIC technology with 0.18 micron L-drawn Overview LSI Logic’s G12 ASIC Cell-Based product, with its three digital libraries, offers unprecedented options for system ASIC designers to optimize their ASIC or

LSI Logic ASIC

Abstract: USB Hub LSI coreware library USB PANEL LSI LOGIC
Contextual Info: USB Hub Core Hub Core for Universal Serial Bus Solutions Overview LSI Logic's USB Hub Core, a component of LSI Logic’s comprehensive Universal Serial Bus USB solution set, is a flexible and configurable core that supports additional USB connections within a USB system, enabling the

011U

Abstract: LSI coreware library ARM11 lsi logic ARM11 "instruction set summary" armv5te cp14 ARM coprocessor
Contextual Info: DATASHEET 0.11µ ARM966E-S Processor cw001163_1_0 October 2004 Preliminary DB08-000257-00 This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the functional descriptions, or the electrical and mechanical specifications using

ARMv5TE instruction set

Abstract: ARM946E-STM ARMv5TE ARM946E-S ARM processor data flow design flow soc architecture ARM966E-S CW001100 TCMS
Contextual Info: CW001100 - 200 MHz Synthesized ARM946E-S Core with Cache Memories OVERVIEW FEATURES AND BENEFITS The CW001100 processor core is a 200 MHz implementation of the popular ARM946E-S™, synthesized onto LSI Logic’s G12P 0.18 micron high performance process technology.

design flow soc architecture

Abstract: ARM processor data flow ARM9E-S ARM9E-STM ARM966E-S CW001105 ARMv5TE instruction set ARMv5TE LSI cell library
Contextual Info: CW001105 - 200 MHz Synthesized ARM966E-S Core OVERVIEW FEATURES AND BENEFITS The CW001105 processor core is a 200 MHz implementation of the popular ARM966E-S™, synthesized onto LSI Logic’s G12P 0.18 micron high performance process technology. • 200 MHz Operating frequency