MIPS Search Results

TMS320P17

Abstract: d6151 filter lark eng 1D2T ltw 8 pin TMS320P14 TMS320LC15
Contextual Info: TMS320C1X DIGITAL SIGNAL PROCESSORS J A N U A H Y 1 9 8 7 — R E V IS E D J U L Y 1991 • Performance Up to 8.77 MIPs Commercial and Military Versions Available • All TMS320C1x Devices are Object Code Compatible Operating Free-Air Temperature . . . 0°C to 70°C

Contextual Info: TM Diplomat -E Device Programmable Ethernet Network Processor TXC-06877 PRODUCT INFORMATION APPLICATIONS • Programmable Ethernet Network Processor with 900 MIPS of packet processing performance • eNPU packet processor firmware programmed in C-language allows for rapid

Contextual Info: TMS320LF2407, TMS320LF2406, TMS320LF2402 DSP CONTROLLERS SPRS094E – APRIL 1999 – REVISED AUGUST 2000 D High-Performance Static CMOS Technology D D D D D External Memory Interface LF2407 – 33-ns Instruction Cycle Time (30 MHz) – 30 MIPS Performance

Contextual Info: BCM3349 ADVANCED QAMLINK® DOCSIS® 2.0 HIGH-PERFORMANCE, SINGLE-CHIP CABLE MODEM SUMMARY OF BENEFITS FEATURES • DOCSIS®/EuroDOCSIS 2.0 cable modem providing unprecedented levels of integration and performance • The BCM3349 integrates: • High performance 200 MHz MIPS32™ CPU

c4460

Abstract: TMSC44 TMS320C40GFL Texas Instruments processor selection guide 1994 120M 336M LD31 TMS320C44 TMS320C44-50 TMS320C44-60
Contextual Info: TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 D Highest Performance Floating-Point Digital D D D D D D D D D Signal Processor DSP − TMS320C44-60: 33-ns Instruction Cycle Time, 330 MOPS, 60 MFLOPS, 30 MIPS, 336M Bytes/s

MSP50C614

Abstract: SPSU014 P614
Contextual Info: MSP50C614 MIXED-SIGNAL PROCESSOR SPSS023C – DECEMBER 1999 – REVISED FEBRUARY 2001 D D D D D D D D D Advanced, Integrated Speech Synthesizer for High-Quality Sound. Operates up to 12.32 MHz Performs up to 12 MIPS Single-Chip Solution for up to 6.8 Minutes

MSP50C614

Abstract: SPSU014 C614 P614
Contextual Info: MSP50C614 MIXEDĆSIGNAL PROCESSOR ą ąą SPSS023B – DECEMBER 1999 – REVISED MAY 2000 D Advanced, Integrated Speech Synthesizer D D D D D D D D for High-Quality Sound. Operates up to 12.32 MHz Performs up to 12 MIPS Very Low-Power Operation, Ideal For

AT91 TC CAPTURE

Abstract: AT91FR40162
Contextual Info: Features • Incorporates the ARM7TDMI ARM® Thumb® Processor Core • • • • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE In-circuit Emulation

0.18-um CMOS technology characteristics

Abstract: C6203 SN0042 5962-0051001QXA SMJ320C6203 SMJ320C6203GLPM17 SN00372GLG fpm 250 airflow DSP sdram military
Contextual Info: Fact Sheet M i l i t a r y S e m i c o n d u c t o r PRODUCT PREVIEW P r o d u c t s SMJ320C6203GLPM17 / 5962-0051001QXA August 2000 1400 MIPS 16-BIT FIXED POINT DSP DIGITAL SIGNAL PROCESSOR HIGHLIGHTS The SMJ320C6203 DSP is a member of the SMJ320C62x fixed-point DSP family in the SMJ320C6000

bass treble circuit schematic

Abstract: TDA7502 TDA7535 TQFP44
Contextual Info: TDA7502 IN-CAR REMOTE AMPLIFIER DSP • ■ ■ ■ ■ ■ ■ ■ ■ 24-Bit FIXED-POINT DSP CORE DELIVERING UP TO 50 MIPS 2 x 1024 x 24 Bit OF RAM FOR X AND Y DATA MEMORY. 3072 x 24 Bit OF RAM FOR PROGRAM ALSO USABLE FOR DELAY SERIAL AUDIO INTERFACE. DEBUG PORT.

R4000

Abstract: R4640 R4650 R4700 R5000 RM5230TM R5000 mips MIPS RM5230
Contextual Info: RM5230 Superscalar Microprocessor with 32-Bit System Bus FEATURES • Dual Issue superscalar microprocessor — 100, 133, 150 and 175 MHz operating frequencies — 210 Dhrystone2.1 MIPS — SPECInt95 3.5, SPECfp95 3.7 • System interface optimized for embedded applications

EAXXX

Contextual Info: TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 D Highest Performance Floating-Point Digital D D D D D D D D D Signal Processor DSP − TMS320C44-60: 33-ns Instruction Cycle Time, 330 MOPS, 60 MFLOPS, 30 MIPS, 336M Bytes/s

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD98502 NETWORK CONTROLLER The µPD98502 network controller is an LSI for network terminal applications such as ADSL systems. The controller integrates a VR4120A MIPS RISC CPU core, memory interface, PCI, and other network interface

79RC32351

Abstract: FIPS-140 MIPS32 RC32351 RC32355 RC32365 RC32434 RC32438
Contextual Info: IDT Interprise™ Integrated Communications Processor PRODUCT FAMILY IDT™ Interprise™ processors for enterprise and broadband access networks The IDT™ Interprise™ family of integrated communications processors and development tools are based on the MIPS instruction set

LR3000

Abstract: LR3020 bit-slice
Contextual Info: 4 LSI Logic Corporation LR3020 W rite Description ISSI McCarthy Blvd. Milpitas, CA 95035 4 0 S .4 3 3 .8 0 0 0 Buffer Advance Information The LR3020 write buffer enhances performance o f MIPS architecture based systems by allowing the processor to perform write operations durine run

8051 pca capture frequency

Abstract: C8051F310 CIP-51
Contextual Info: C8051T614 25 MIPS, 8 kB EPROM, Mixed-Signal MCU Analog Peripherals High-Speed 8051 µC Core - Comparator - Programmable hysteresis and response time - Configurable as interrupt or reset source Low current < 0.5 µA 1280 bytes internal data RAM 8kB byte-programmable EPROM code memory

Contextual Info: TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 D Highest Performance Floating-Point Digital D D D D D D D D D Signal Processor DSP − TMS320C44-60: 33-ns Instruction Cycle Time, 330 MOPS, 60 MFLOPS, 30 MIPS, 336M Bytes/s

C8051F060DK

Abstract: C8051F066
Contextual Info: C8051F066 25 MIPS, 32 kB Flash, 16-Bit ADC, 100-Pin Mixed-Signal MCU Analog Peripherals High-Speed 8051 µC Core - Two 16-Bit ADCs - ±0.75 LSB INL; no missing codes Programmable throughput up to 1 Msps each ADC 1 external input each; programmable as two single-ended or one differential ADC

C8051F352

Abstract: C8051F350DK 16bit adc mcu
Contextual Info: C8051F352 50 MIPS, 8 kB Flash, 16-Bit ADC MCU PRELIMINARY ANALOG PERIPHERALS HIGH-SPEED 8051 µC Core 16-BIT ADC - No missing codes - 0.002% nonlinearity - Programmable conversion rates up to 1 ksps - 1x to 128x PGA - 8 input multiplexer - Built-in temperature sensor

Contextual Info: TMS320VC5420 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 D 200-MIPS Dual-Core DSP Consisting of Two D D D D D D D D D D D D D Independent Subsystems Each Core Has an Advanced Multibus Architecture With Three Separate 16-Bit

C4460

Contextual Info: TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 D Highest Performance Floating-Point Digital D D D D D D D D D Signal Processor DSP − TMS320C44-60: 33-ns Instruction Cycle Time, 330 MOPS, 60 MFLOPS, 30 MIPS, 336M Bytes / s

TMS320P14

Abstract: TMS320LC15
Contextual Info: TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 • • • • • • • • • • • • • • • Performance Up to 8.77 MIPs • • All TMS320C1x Devices are Object Code Compatible 144/256-Word On-Chip Data RAM

TMS320P14

Abstract: TMS320LC15
Contextual Info: TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 • • • • • • • • • • • • • • • Performance Up to 8.77 MIPs • • All TMS320C1x Devices are Object Code Compatible 144/256-Word On-Chip Data RAM

T801

Abstract: speedo meter N10E inmos transputer T800 TIN30 T800 transputer T801-20 2AF3 w188
Contextual Info: 127 IMS T801 transputer □ Preliminary Data FEATURES 32 bit architecture 33 ns internal cycle time 30 MIPS peak instruction rate 4.3 Mflops (peak) instruction rate Debugging support 64 bit on-chip floating point unit which conforms to IEEE 754 4 Kbytes on-chip static RAM