CLS189 Search Results

74ls189 ram

Abstract: 74LS189 74LS189 logic diagram 74LS189DC 74LS189PC 74LS189FC 74S189DC 54LS189DM 54S189DM 74S189FC
Contextual Info: 189 CONNECTION DIAGRAM PINOUT A ¡4S/74S189 ►54LS/74LS189 b n 7 S 0 ao [T ï i ] Vcc 64-BIT RANDOM ACCESS MEMORY C sU m a. With 3-State Outputs we |T T7| A2 Di [7 Ö1 [ ? j l ] A3 02 ï D ESC R IPTIO N — The '189 is a high speed 64-bit RAM organized as a 16word by 4 -b it array. Address inputs are buttered to m inimize loading and are

Contextual Info: SN54LV74, SN74LV74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SC LS 189C - FEBRUARY 1993 - REVISED APRIL 1986 EPIC Enhanced-Performance Implanted CMOS 2-|i Process Typical V q l p (Output Ground Bounce) < 0.8 V at VCc. Ta = 25°C Typical V q h v (Output Voh Undershoot)

74ls189 ram

Abstract: 74LS189 74LS189 logic diagram 74LS189DC 54LS189DM 74LS189PC ls189 54S189DM 74LS189FC 74S189DC
Contextual Info: 189 C O N N E C T IO N D IA G R A M P IN O U T A ¡4S/74S189 l54L S/74L S189 b / / 7 S ö 6 4 -B IT R A N D O M A C C E S S M EM O R Y With 3-S tate O utputs a 0[T 16] V cc c s |X H A, WE j T î7 | A2 Di [ 7 i l ] A3 öl [7 T 2I d 4 d2 ï T|04 [b To] d 3

74LS189

Abstract: CS-189
Contextual Info: N A T IO N A L S E M IC Ô ND {LO GIC} OSE D I bSO llSE O O t^ ll 2 I 189 C O N N E C T IO N D IA G R A M P IN O U T A 54S/74S189 54LS/74LS189 i— r 1— A o [T T|] V cc 64-BIT RANDOM ACCESS MEMORY c s[T TT| At With 3-State Outputs W l[ ? 75] a 2 D i [4