CLOCK SYNCHRONIZATION Search Results

DIP28

Abstract: PLCC28 TS68950 TS68951 TS68952 TS68952CFN TS68952CP programming controle system with c rc711
Contextual Info: TS68952 MODEM TRANSMIT/RECEIVE CLOCK GENERATOR . . . . . . INDEPENDANT TRANSMIT AND RECEIVE CLOCK GENERATORS WITH DIGITAL PHASE LOCKED LOOPS TRANSMIT DPLL SYNCHRONIZATION ON EXTERNAL TERMINAL CLOCK OR INTERNAL RECEIVE CLOCK RECEIVE DPLL SYNCHRONIZATION CONTROLLED FROM THE BUS

TDC 8117

Abstract: TS68952CP
Contextual Info: TS68952 MODEM TRANSMIT/RECEIVE CLOCK GENERATOR . . . . . . INDEPENDANT TRANSMIT AND RECEIVE CLOCK GENERATORS WITH DIGITAL PHASE LOCKED LOOPS TRANSMIT DPLL SYNCHRONIZATION ON EXTERNAL TERMINAL CLOCK OR INTERNAL RECEIVE CLOCK RECEIVE DPLL SYNCHRONIZATION CONTROLLED FROM THE BUS

DS31400

Abstract: APP4391 DS3100 DS3101 DS3102 DS3104 DS3105 GR-1244-CORE phase failure protection IC
Contextual Info: Maxim > App Notes > Communications circuits Keywords: stratum 3, stratum 3E, stratum 4E, G.813, G.812, clock, clock sync, clock synchronization, timing card, timing IC, DPLL, master- Apr 03, 2009 slave, redundancy, telecom, SONET, SDH, clock sync, sonet, sdh, equipment protection, synchronous ethernet

APP4391

Abstract: DS3100 DS3101 DS3102 DS3104 DS3105 GR-1244-CORE
Contextual Info: Maxim > App Notes > Communications Circuits T/E Carrier and Packetized Keywords: stratum 3, stratum 3E, stratum 4E, G.813, G.812, clock, clock sync, clock synchronization, timing card, timing IC, DPLL, master-slave, redundancy, telecom, SONET, SDH, clock sync, sonet, sdh, equipment

ac phase ac 400 v detector

Abstract: CY2210 CY2211
Contextual Info: PRELIMINARY CY2211 Direct Rambus Clock Generator Features Benefits • High Speed Clock Support Provides 400-MHz differential clock source for Direct Rambus memory systems for an 800-MHz data transfer rate. • Synchronization Flexibility The CY2211 includes signals to synchronize the clock domains of the

74AHCT193

Abstract: SEL24 XRT8000 XRT8001 XRT8001ID XRT8001IP 128KHZT
Contextual Info: XRT8001 WAN Clock for T1 and E1 Systems March 2001-1 • Generates Output Clock Frequencies Ranging GENERAL DESCRIPTION The XRT8001 WAN Clock is a dual-phase-locked loop chip that generates two very low jitter output clock signals that can be used for synchronization clocks in

Contextual Info: XRT8001 WAN Clock for T1 and E1 Systems October 2001-1 GENERAL DESCRIPTION • Generates Output Clock Frequencies Ranging The XRT8001 WAN Clock is a dual-phase-locked loop chip that generates two very low jitter output clock signals that can be used for synchronization clocks in

SEL24

Abstract: XRT8000 XRT8001 XRT8001ID XRT8001IP
Contextual Info: XRT8001 WAN Clock for T1 and E1 Systems October 2001-1 GENERAL DESCRIPTION • Generates Output Clock Frequencies Ranging The XRT8001 WAN Clock is a dual-phase-locked loop chip that generates two very low jitter output clock signals that can be used for synchronization clocks in

M88TS

Abstract: TS68952CFN TS68950-51-52 rca 210 BAT43 TS68950 TS68951 TS68952 rc711 ARC-3
Contextual Info: S G S -T H O M S O N TS68952 !L [E O T riE @ [M D D Ì MODEM TRANSMIT/RECEIVE CLOCK GENERATOR • INDEPENDANT TRANSMIT AND RECEIVE CLOCK GENERATORS WITH DIGITAL PHASE LOCKED LOOPS ■ TRANSMIT DPLL SYNCHRONIZATION ON EXTERNAL TERMINAL CLOCK OR INTERNAL RECEIVE CLOCK

CH9073

Contextual Info: 101 CH9073 CHRONTEL Preliminary Video Genlock Pixel Clock Generator Features Description • On-chip PLL for clock synchronization CH 9073 is a PLL clock generator designed to provide the necessary implementation o f a video genlock pixel clock generator. It consists o f a phase detector, a charge

V20 70108

Contextual Info: UMC UM82C94 ^ S S S S S E CMOS Clock Generator Driver £ E Features • Generates the system clock for V-20 Microprocessor ■ Capable of clock synchronization with other clock ■ Up to 20 MHz operation generators ■ Uses a parallel mode crystal circuit or external frequency

AT43USB320A

Abstract: AT43USB325 AT43USB326 AT43USB351M AT43USB353M AT43USB355
Contextual Info: Errata All Date Codes : Missed Watchdog Timer Reset Problem There is a synchronization problem between the watchdog clock and the AVR clock. Even though the clock inputs to both the watchdog timer and the AVR core are generated through the same crystal, the two clock sources are not going through the same

Contextual Info: CDC2582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS _SCAS379B - FEBRUARY 1993 - REVISED FEBRUARY 1996 Low Output Skew for Clock-Dlstrlbutlon and Clock-Generatlon Applications Operates at 3.3-V Vcc Distributes Differential LVPECL Clock

Contextual Info: CDC582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS _ SCAS446B - JULY 1994- REVISED FEBRUARY 1996 Low Output Skew for Clock-Dlstrlbutlon and Clock-Generatlon Applications Operates at 3.3-V Vqc Distributes Differential LVPECL Clock

Contextual Info: CDC582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS _ SCAS446B - JULY 1994 - REVISED FEBRUARY 1996 Low Output Skew for Clock-Dlstrlbutton and Clock-Generatlon Applications Operates at 3.3-V Vcc Distributes Differential LVPECL Clock

transistor x1

Abstract: IDT49FCT805 49FCT805A 49FCT806 AN-82 IDT49FCT805A IDT49FCT806 IDT74FCT244A
Contextual Info: CLOCK DISTRIBUTION SIMPLIFIED WITH IDT GUARANTEED SKEW CLOCK DRIVERS  Integrated Device Technology, Inc. APPLICATION NOTE-82 CLOCK DISTRIBUTION SIMPLIFIED WITH IDT GUARANTEED SKEW CLOCK DRIVERS APPLICATION NOTE AN-82 By Michel Conrad INTRODUCTION WHAT IS CLOCK SKEW ?

Contextual Info: CDC2582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS _SCAS379B- FEBRUARY 1993 - REVISED FEBRUARY 1996 • • Low Output Skew or Clock-Distrlbutlon and Clock-Generatlon Applications Operates at 3.3-V Vcc Distributes Differential LVPECL Clock

Contextual Info: CDC2582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS SCAS379 - FEBRUARY 1993 - REVISED MARCH 1994 Low Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V V cc Distributes Differential LVPECL Clock

Contextual Info: DATA SHEET ICS661 ICS661 Precision Audio Clock Source Precision Audio Clock Source Description Features The ICS661 provides synchronous clock generation for audio sampling clock rates derived from an MPEG stream, or can be used as a standalone clock source

ZL30155

Abstract: KEY 10g zl3015 10GBASE-R simple block diagram for digital clock
Contextual Info: DUAL CHANNEL UNIVERSAL CLOCK TRANSLATOR ZL30155 PRODUCT PREVIEW The ZL30155 Dual Channel Universal Clock Translator, part of Zarlink’s ClockCenter platform of Synchronous Clock devices, delivers industry-leading synchronization performance for high-speed complex applications. The highly integrated

ZL30155

Contextual Info: DUAL CHANNEL UNIVERSAL CLOCK TRANSLATOR ZL30155 PRODUCT PREVIEW The ZL30155 Dual Channel Universal Clock Translator, part of Zarlink’s ClockCenter platform of Synchronous Clock devices, delivers industry-leading synchronization performance for high-speed complex applications. The highly integrated

93V855A

Contextual Info: ICS93V855 Integrated Circuit Systems, Inc. DDR Phase Lock Loop Clock Driver Recommended Application: DDR Clock Driver Pin Configuration Product Description/Features: • Low skew, low jitter PLL clock driver • External feedback pins for input to output synchronization

TDM 5510

Abstract: 5501 7 segment
Contextual Info: Application Note MSAN-171 TDM Clock Recovery from CBR-OverATM Links Using the MT90500 ISSUE 1 Contents 1. 2. 3. 4. 5. 6. 7. Introduction Plesiochronous Clock Applications Generalized Clock Recovery Synchronous Method Physical Layer Clock Adaptive Clock Recovery Method

DS21610

Abstract: DS21610QN DS21610SN LXP610 TR62411 direct replacement
Contextual Info: DS21610 Clock Rate Adapter www.maxim-ic.com FEATURES Direct replacement for LXP610SE Converts E-carrier clock rates to T-carrier clock rates Converts T-carrier clock rates to E-carrier clock rates Low jitter output Multiple output clocks synchronized to input