CHARACTERISTICS15 Search Results

A12C

Abstract: A14C A15C CY62127V
Contextual Info: CY62127V V CYPRESS 64K x 16 Static RAM Writing to the device is accomplished by taking Chip Enable CE and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (l/0-| through l/0 8), is written into the location specified on the address pins (Aq

82440LX

Contextual Info: fax id: 3535 CYPRESS ë CY2276-2 CY2276-3 CY2276-4 PRELIMINARY Pentium II Clock Synthesizer/Driver for Intel 82440LX Chipset with 3 or 4 DIMM and USB/IO Support of outputs available from each device, as shown in the Selec­ tor Guide. Features • Mixed 2.5V and 3.3V operation

84 PIN CERAMIC QUAD FLAT PACK

Abstract: 2600 corning cypress flash 370 7C374-100 7C374-66 7C374L-66 CY7C373 CY7C374 FLASH370 CY7C374-83GC
Contextual Info: fax id: 6129 —— — - = : ! W Æ j r I 1 CY7C374 17 Q Q IT C O O UltraLogic 128-Macrocell Flash CPLD Features The logic blocks in the FLASH370 architecture are connected with an extremely fast and predictable routing resource— the Programmable Interconnect Matrix PIM . The PIM brings flex­

CY2282-1

Abstract: CY2282-11S DD25
Contextual Info: CY2282-1 CY2282-11S PRELIMINARY r'YPRFÇÇ 10O-MHz Pentium II Clock Synthesizer/Driver with Spread Spectrum and USB for Desktop PCs Features 3.3 V USB clocks at 48 MHz, one 3.3 V reference clock at 14.318 M Hz, and one 2 .5 V A P IC clo ck at 14.318 MHz.

Contextual Info: fax id: 3531 CYPRESS PRELIMINARY CY2030 USB, Audio, and I/O Clock Generator for Intel 82440LX Chipset Features Functional Description • USB, Audio, and I/O clock generator for most m other­ boards using 5th or 6th generation processors. Can also be used for peripheral systems.

Contextual Info: fax id: 3557 A CY2282-1 CY2282-11S PRELIMINARY 100-MHz Pentium II Clock Synthesizer/Driver with Spread Spectrum and USB for Desktop PCs Features 3.3V USB clocks at 48 MHz, one 3.3V reference clock at 14.318 MHz, and one 2.5V APIC clock at 14.318 MHz. • Mixed 2.5V and 3.3V operation

l83A

Contextual Info: fax id: 6126 CY7C371 CYPRESS UltraLogic 32-Macrocell Flash CPLD FLASH370 fam ily the CY7C371 is designed to bring the ease of use and high performance of the 22V10 to high-density CPLDs. Features • 32 macrocells in two logic blocks • 32 I/O pins The 32 macrocells in the CY7C371 are divided between two

Contextual Info: fax id: 3549 * - ' vv . « ¿ ¿ A * CY2286 <J8WF Pentium II and K6 Clock Synthesizer/Driver with 100 MHz, AGP, 4 DIMM and USB/IO Support • F acto ry -E P R O M p ro g ram m ab le clo c k fre q u e n c ie s fo r custom c o n fig u ra tio n s Featu res

UC006

Abstract: SS13 EVAL-ADuC836QS
Contextual Info: MicroConverter , Dual 16-Bit - ADCs with Embedded 62 kB Flash MCU ADuC836 FEATURES High Resolution - ADCs 2 Independent ADCs 16-Bit Resolution 16-Bit No Missing Codes, Primary ADC 16-Bit rms (16-Bit p-p) Effective Resolution @ 20 Hz Offset Drift 10 nV/C, Gain Drift 0.5 ppm/C

P80A49H

Abstract: 8035HL F1L 250 V fuse BPK-70 interfacing 8275 crt controller with 8086 i8282 hall marking code A04 Transistor AF 138 DK55 82720 intel
Contextual Info: COMPONENT DATA CATALOG JANUARY 1982 Intel C orporation makes no w arranty fo r the use of its products and assumes no re sponsib ility fo r any e rrors w hich may appear in th is docum ent nor does it make a com m itm ent to update the info rm atio n contained herein.

A12C

Abstract: A14C A15C CY62127V
Contextual Info: CY62127V V CYPRESS 64K x 16 Static RAM Writing to the device is accomplished by taking Chip Enable CE and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (l/0-| through l/0 8), is written into the location specified on the address pins (Aq

Contextual Info: CY7B326 PRELIMINARY CYPRESS SEMICONDUCTOR Multipurpose BiCMOS PLD Features Functional Description • 16 I/O macrocells, each having: — Program m able com binatorial syn­ chronous and asynchronous modes — Registers configurable to T-type and D-type — Array feedback from I/O pin or

62512 RAM 64k x 8

Abstract: 62512 RAM CY62512V CY62512VLL-70ZC 62512 A12C A14C A15C
Contextual Info: fax id: 1098 CY62512V PRELIMINARY W OYPHESS 64K x 8 Static RAM Features er-dow n fea tu re that reduces po w e r con sum p tion by m ore tha n 99 % w h en deselected. • 2 .7 V -3 .6 V o peratio n W riting to the device is accom plished by taking chip enable

cypress flash 370

Abstract: 7C375-83 7C375L-66 CY7C375 FLASH370
Contextual Info: fax id: 6130 —— — Æ jr r ~ 'f V D D 1 7 Q CY7C375 Q I 1 IT COO UltraLogic 128-Macrocell Flash CPLD Features o f use and high pe rfo rm an ce of th e 22V 10 to high -den sity PLDs. • 28 macrocells in eight logic blocks • 28 I/O pins • 6 dedicated inputs including 4 clock pins

CY2286PVC-1

Abstract: CY2286PVC-2 CY2288 7X7C
Contextual Info: fax id: 3549 ADVANCED INFORMA TION C Y 2 2 8 6 Pentium II and K6 Clock Synthesizer/Driver with 100 MHz, AGP, 4 DIMM and USB/IO Support Features • Factory-EPROM programmable clock frequencies for custom configurations • Low CPU clock jitter < 250 ps cycle-cycle.

Contextual Info: CY2282-1 CY2282-11S PRELIMINARY 10O-MHz Pentium II Clock Synthesizer/Driver with Spread Spectrum and USB for Desktop PCs 3.3V USB clocks at 48 MHz, one 3.3V reference clock at 14.318 MHz, and one 2.5V APIC clock at 14.318 MHz. Features • Mixed 2.5V and 3.3V operation

cy2260sc-3

Contextual Info: fax id: 3520 CY2260 Clock Synthesizer/Driver for Pentium and Pentium Pro™ Processors • 3.3V or 5V operation • Internal pull-up resistors on SO, S1, and OE inputs Features • Multiple clock outputs to meet requirements of most motherboards using Pentium™ , Pentium Pro™, or

Contextual Info: fax id: 3520 *ÍK&8b'' CY2260 Clock Synthesizer/Driver for Pentium and Pentium Pro™ Processors Featu res • 3.3V or 5V o peratio n • Intern al p ull-up re sisto rs on SO, S1, and O E inputs • M u ltip le clo c k o utp uts to m eet re q u ire m en ts of m ost

Contextual Info: fax id: 1082 W CYPRESS PRELIMINARY 512Kx 8 Static RAM is provided by an active LOW chip enable CE , an active LOW output enable (OE), and three-state drivers. Writing to the de­ vice is accomplished by taking chip enable (CE) and write en­ able (WE) inputs LOW. Data on the eight I/O pins (l/O0 through

Contextual Info: CY7C1049V33 CYPRESS_ Features 512Kx 8 Static RAM sion is provided by an active LO W C hip Enable CE , an active LO W O utput Enable (O E), and th re e -sta te drivers. W riting to th e de vice is a c c o m plished by ta kin g C hip Enable (CE) and W rite Enable (W E) inputs LOW. D ata on the e igh t I/O pins (l/O 0

Contextual Info: fax id: 1099 CY62127V PRELIMINARY ¿up P Y P R F ^ R \œt*> J : JT J» l i j f e s J t s J 64K x 16 Static RAM Features Writing to the device is accomplished by taking chip enable CE and write enable (WE) inputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins (l/0-| through l/Og), is

Contextual Info: fax id: 3542 •s "" ' CY2276A-12 SS CY2276A-13 Pentium@ll Clock Synthesizer/Driver for Desktop PCs with Intel 82440LX and 4 DIMMs Features • Mixed 2.5V and 3.3V operation • Com plete clock solution to meet requirem ents of Pen­ tium ® and Pentium® II motherboards

Contextual Info: fax id: 1098 CY62512V PRELIMINARY 64K x 8 Static RAM Features er-dow n feature th a t reduces po w e r con sum p tion by m ore than 99% w h en deselected. • 2 .7 V -3 .6 V o p eratio n W riting to th e device is acco m plishe d by takin g chip enable one CE-| and w rite enable (W E) inputs LOW and chip enable

CY62127V

Contextual Info: fax id: 1100 CY62126V PRELIMINARY 64K x 16 Static RAM Features BLE is LOW, then data from I/O pins (l/0-| through l/Og), is written into the location specified on the address pins (A0 through A 15). If byte high enable (BHE) is LOW, then data from I/O pins (l/Og through l/0 -|g) is written into the location speci­