CERAMIC PIN GRID ARRAY 120 PINS Search Results

Contextual Info: Package outline SOT259-2 CPGA120: ceramic pin grid array package; 120 pins; body 33.5 x 33.5 x 2.6 mm D D1 pin 1 index mark location A2 E1 E A1 L detail X b e N e M L K J H G F index pin E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 X seating plane DIMENSIONS mm dimensions are derived from the original inch dimensions

PGA144

Abstract: 144 PGA 144 pin pga 81F64842B Atmel DATE CODE PGA-120 PGA 84 PGA84 PGA120
Contextual Info: 68 pins PGA Ceramic Pin Grid Array PGA Package Outlines Code:8M Date: 15/12/95 Rev. B – 23/08/01 1 PGA 84 pins PGA Code 8R Date: 21/07/00 2 Rev. B – 23/08/01 100 pins PGA Code:GT Date: 14/06/00 3 PGA Rev. B – 23/08/01 PGA 120 pins PGA Code:GU Date: 25/06/99

c3466

Abstract: C3461 C3467 b4 c346 diode c346 diode IC 7400 SERIES ALL DATA C346 CY7C346 CY7C346B c3468
Contextual Info: fax id: 6104 1CY 7C34 6B CY7C346 CY7C346B 128-Macrocell MAX EPLDs Features ture is 100% user configurable, allowing the devices to accommodate a variety of independent logic functions. • • • • 128 macrocells in 8 LABs 20 dedicated inputs, up to 64 bidirectional I/O pins

Contextual Info: CY7C346 CY7C346B CYPRESS 128-Macrocell M AX EPLD Features Functional Description • 128 macrocells in 8 LABs • 20 dedicated inputs, 64 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C346

VMEbus interface handbook

Abstract: transistors BC 543 Cypress VMEbus Interface Handbook diode 68A VAC068 VIC068A LA18 14 pin ld18 transistor BC 147 FCT245
Contextual Info: fax id: 5600 1V AC0 68A VAC068A VMEbus Address Controller Features — Supports unaligned transfers • Optional companion part to VIC068A • Implements master/slave VMEbus interface in conjunction with the VIC068A • Complete VMEbus and I/O DMA capability for a 32-bit

LE C346

Abstract: 5067B
Contextual Info: fax id: 6104 CY7C346 CY7C346B 128-Macrocell MAX EPLDs ture is 100% user configurable, allowing the devices to accom ­ modate a variety of independent logic functions. Featu res • 128 macrocells in 8 LABs • 20 dedicated inputs, up to 64 bidirectional I/O pins

VIC068A

Abstract: VAC068 VAC068A FCT245 106240 ld18 LD31 LBR 84 VMEbus interface handbook
Contextual Info: VAC068A VMEbus Address Controller Features — Supports unaligned transfers • Optional companion part to VIC068A • Implements master/slave VMEbus interface in conjunction with the VIC068A • Complete VMEbus and I/O DMA capability for a 32-bit CPU • Complete local and VMEbus memory map decoding

PI011

Contextual Info: . VAC068A mmàà^SSSSSSSSrnfi * .ài*' /*? / c VMEbus Address Controller • Dual UART channels on board — Double-buffered on transmit, quint-buffered on receive — Baud rate programmable • Miscellaneous features — Pin grid array or quad flatpack

ld18 st

Abstract: VME ACFAIL cypress VMEbus Interface handbook dio ld26
Contextual Info: fax id: 5600 VAC068A VMEbus Address Controller — Supports unaligned transfers Featu res • Optional companion part to VIC068A • Implements master/slave VMEbus interface in conjunc­ tion with the VIC068A • Complete VMEbus and I/O DMA capability for a 32-bit

ceramic pin grid array package plating

Contextual Info: Standard Products RadHard Eclipse FPGA Family 6250 and 6325 Advanced Data Sheet May, 2005 www.aeroflex.com/RadHardFPGA FEATURES ‰ Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation ‰ QuickLogic IP available for microcontrollers, DRAM

Contextual Info: LSI LOCK L64210/L64211 Variable-Length Video Shift Registers The L64210 and L64211 are two high-speed Variable-Length Video Shift Registers. These devices can be used individually or as video line delays for the L64200 series filter proces­ sors. Description

CY37064P44-154YMB

Abstract: CY37512P208-100UMB CY37256P160-125UMB CY37032 CY37032V CY37064 CY37064V CY37128 CY37128V CY37032VP44-100AI
Contextual Info: Family Ultra37000 CPLD Family[1] 5V, 3.3V, ISR™ High-Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

CX3001

Abstract: CX3000 "CHIP EXPRESS" CX3002 2308 rom CHIPX PQFP ALTERA 160 mentor graphics pads layout ambit circuit CX300
Contextual Info: 15244 ChipExpress W/Tumble Black cyan m a g yellow www.chipexpress.com Chip Express products are protected by one or more of the following U.S. patents: . This information is subject to change without notice. CX3000, HardArray, OneMask, and

CY37032P44-154AXI

Abstract: CY37128P160-125AC 5962-9951902QYA CY37032 CY37032V CY37064 CY37064V CY37128 CY37128V CY37192
Contextual Info: Ultra37000 CPLD Family 5V, 3.3V, ISR High-Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes

5962-9951902QYA

Abstract: CY37128P100-125AXC U208 5962-9952301QZC CERAMIC LEADLESS CHIP CARRIER CY37032P44-125JXC CY37512P256-100BGI CY37192 CY37256 CY37384
Contextual Info: Ultra37000 CPLD Family 5V, 3.3V, ISR High-Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes

Contextual Info: CY7C342 CY7C342B CYPRESS SEMICONDUCTOR & 128-Macrocell M A X EPLDs Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • Available in 68-pin HLCC, PLCC, PGA, and Flatpack

pin diagram of 74381

Abstract: N335
Contextual Info: www.fairchildsemi.com TMC2246A Image Filter 11 x 10 bit, 60 MHz Features Applications • • • • • • • • • • • • • 60 MHz computation rate 60 MHz data and coefficient input Four 11 x 10-bit multipliers Individual data and coefficient inputs

CY37064

Abstract: ULTRA37000 CY37032 CY37032V CY37064V CY37128 CY37128V CY37192 CY37256 CY37384
Contextual Info: Ultra37000 CPLD Family 5V, 3.3V, ISR High-Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes

Contextual Info: LSI LOGIC L64210/L64211 Variable-Length Video Shift Registers Prelim inary Description The L64210 and L64211 are two high-speed Variable-Length Video Shift Registers. These devices can be used individually or as video line delays for the L64200 series filter processors.

64 pin CERAMIC QUAD FLATPACK

Contextual Info: Standard Products RadHard Eclipse FPGA Advanced Data Sheet August, 2004 www.aeroflex.com/RadHardFPGA ‰ Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation ‰ QuickLogic IP available for microcontrollers, DRAM controllers, USART and PCI

CERAMIC QUAD FLATPACK CQFP 96

Contextual Info: Standard Products RadHard Eclipse FPGA Advanced Data Sheet September, 2004 www.aeroflex.com/RadHardFPGA ‰ Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation ‰ QuickLogic IP available for microcontrollers, DRAM controllers, USART and PCI

Contextual Info: EEPROM AS8E128K32 128K x 32 EEPROM PIN ASSIGNMENT EEPROM Memory Array Top View 66 Lead PGA AVAILABLE AS MILITARY SPECIFICATIONS • • (Pins 8, 21, 28, 39 are no connects on the PN package) SMD 5962-94585 MIL-STD-883 FEATURES OPTIONS • • 66 Lead PGA

208-Pin CQFP

Abstract: CLGA smd M16
Contextual Info: Standard Products RadHard Eclipse FPGA Family 6250 and 6325 Data Sheet August 22, 2006 www.aeroflex.com/RadHardFPGA FEATURES ‰ Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation ‰ QuickLogic IP available for microcontrollers, DRAM

Contextual Info: Standard Products RadHard Eclipse FPGA Family 6250 and 6325 Advanced Data Sheet July 2005 www.aeroflex.com/RadHardFPGA FEATURES ‰ Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation ‰ QuickLogic IP available for microcontrollers, DRAM