CC OWV W Search Results

2SC2100

Abstract: 12ID 2j 20T
Contextual Info: 5 /U 3 y N P N ie ?*5 /? l/7 ls-î& h 7 y 5 > Z SILICON NPN EPITAXIAL PLANAR TRANSISTC O 2.0~ 30 M Hzìf SSB « S * « * « O 2.0~30M H z SSB A pplications Linear High L o w Supply (fë«EES8Sffl ) Power V oltage Amplifier Use) • 2 8M Hz-C5 5 W (P E P « $ ffitJ

HM10474

Abstract: 43583 HM10474-10
Contextual Info: HM10474-8,HM10474-10 1024-word x 4-bit Fully Decoded Random Access Memory The H M 10474 is E C L 10k compatible, 1024-words x 4-bit, read write, random access memory developed for high speed systems such as scratch pads and control/buffer storages. The fabrication process is the Hitachi's low capacitance, oxide

cd 2003 gp

Abstract: 2SC2100 i22d 121 122 opto 2-13B1A
Contextual Info: TOSHIBA •CDISCRETE/OPTO> 9097250 DE j T C H 7a5 Q Q D D n 34 D TO SHI BA <DI S C R E T E / O P T O > 39C 0 1 9 3 ^ SEMICONDUCTOR TO SHIBA T RA N SISTO R 2 S C 2 1 00 N P N E P I T A X I A L PLANAR U lt TECHNICAL DATA O * f S IL IC O N ~ 3 0 M H z iff S S B i I Ü 8 B Î i # S f f l

Contextual Info: T O SH IB A TLP560J TOSHIBA PHOTOCOUPLER GaAs IRED & PHOTO-TRIAC TLP560J TRIAC DRIVER U nit in mm PROGRAMMABLE CONTROLLERS AC-OUTPUT MODULE 3 2 1 T l Tf IT SOLID STATE RELAY 3 TTJ—E 4 The TOSHIBA TLP560J consists of a photo-triac optically coupled to a gallium arsenide infrared em itting diode in a six lead plastic DIP

CY7C199-25PC

Abstract: 2218 8 PIN DIP C19S 7C199-15 7C199-20 7C199-25 CY7C199 CE12U
Contextual Info: St •ss CY7C199 CYPRESS 32K x 8 Static RAM Features Functional Description • High speed — 12 ns • Fast tj>oE T he CY7C199 is a high-perform ance CM OS static RAM organized as 32,768 words by 8 bits. Easy m em ory expansion is provided by an active LO W chip enable

Contextual Info: a iL R E L E A S E Final E le ctrica l S p e c ific a tio n s L i n t i A R LTC1344A . TECHNOLOGY Soft w a re -Se Ie c t a b Ie C a b le T erm inator February 1998 F€RTUR€S DCSCRIPTIOn • Software-Selectable Cable Termination for: RS232 V.28 RS423 (V.10)

Contextual Info: ^EDI EDI88512VA-RP ELECTRONIC DESIGNS, INC 512Kx8Ruggedized Plastic Static Ram 512Kx8 Static RAM CMOS, Monolithic Features EDI's ruggedized plastic 512Kx8 SRAM allows the user to 512Kx8 bit CMOS Static capitalize on the cost advantage of using a plastic com po­

Nippon capacitors

Contextual Info: HB56AW1672E-A Series 16777216-word x 72-bit High Density Dynamic RAM Module HITACHI ADE-203-817A Z Rev. 1.0 Aug. 20, 1997 Description The HB56AW1672E-A belongs to 8-byte DIMM (Dual in-line Memory Module) family, and has been developed an optimized main memory solution for 4 and 8-byte processor applications. The

Nippon capacitors

Contextual Info: HB56UW1672E-A Series 16777216-word x 72-bit High Density Dynamic RAM Module HITACHI ADE-203-822A Z Rev. 1.0 Sep. 17, 1997 Description The HB56UW1672E-A belongs to 8-byte DIMM (Dual in-line Memory Module) family, and has been developed an optimized main memory solution for 4 and 8-byte processor applications. The

Contextual Info: HB56UW1673E-6A/7A 16777216-word x 72-bit High Density Dynamic RAM Module HITACHI ADE-203-575A Z Rev. 1.0 Dec. 24, 1996 Description The HB56UW1673E belongs to 8-byte DIMM (Dual in-line Memory Module) family , and have been developed an optimized main memory solution for 4 and 8-byte processor applications. The

Contextual Info: S P S T SIGNAL PROCESSING TECHNOLOGIES P T 1 1 9 8-BIT, HIGH SPEED D/A CONVERTER FEATURES APPLICATIONS • 275 MWPS Conversion Rate - Version A • 165 MWPS Conversion Rate - Version B • Compatible with the HDAC10181 with Improved Performance • RS-343-A Compatible

Contextual Info: fax id: 6138 CY7C373Ì C'i- UltraLogic 64-Macrocell Flash CPLD • Pin compatible with the CY7C374i Features Functional Description • 64 macrocells in four logic blocks • 64 I/O pins • 5 dedicated inputs including 4 clock pins • In-System Reprogrammable ISR™ Flash technology

level shifter from TTL to CMOS

Abstract: ttl to cmos converter level shifter . CMOS to TTL cmos and ttl circuit design level shifter from TTL to CMOS bidirectional ttl cmos CD40116
Contextual Info: CD40116 Types CMOS High-Speed 8-Bit Bidirectional CMOS/TTL Interface Level Converter Features: • ■ E ight in ve rtin g channels with conversion from V n n to V c c o r Vq c to Vq d 4 V < V d d < 12 V a n d 4 V < \ ' c C < .V d d Three operating modes:

Contextual Info: M MOTOROLA MC 34071 ,2 ,4 ,A MC 33071 ,2 ,4 ,A High Slew R ate, W ide Bandwidth, Single Supply O perational Am plifiers Quality bipolar fabrication with innovative design concepts are em ployed for the MC33071/72/74, MC34071/72/74 series of m onolithic operational

Contextual Info: u f m TECHNOLOGY Softw are-Selectable M ultiprotocol Transceiver August 1996 F€ O TUR€S D C S C R IP T IO n • Software-Selectable Transceiver Supports: RS232, RS449. EIA-530, EIA-530-A, V.35, V.36, X.21 ■ NET1 and NET2 Compliant ■ Software-Selectable Cable Termination Using

Contextual Info: r r u r LTC1343 m TECHNOLOGY S o ftw a re -S e le cta b le M u ltip ro to c o l Transceiver FCRTURCS D C S C R IP TIO n • Software-Selectable Transceiver Supports: RS232, RS449, EIA-530, EIA-530-A, V.35, V.36, X.21 ■ NET1 and NET2 Compliant ■ Software-Selectable Cable Termination Using

Contextual Info: THMY7232F0EG-80 TO SHIBA TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 33,554,432-WORD BY 72-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The TH M Y 7232F0EG is a 33,554,432-w ord by 72-bit synchronous dynam ic RAM m odule co n sistin g o f 18 TC59SM 704FT DRAM s and PLL /R egisters on a printed circuit board.

CMOS 4000B series device

Abstract: DAC87H-CBI-V MIL-STD-863 2010 DAC85 DAC87 DAC87H DAC85H DAC85H-CBI-V DAC85H-CBI-V-BI
Contextual Info: DAC85H DAC87H B U R R -B R O W N I B S ] MILITARY VERSION AVAILABLE DESCRIPTION T hese m onolithic digital-to-analog converters are p in-for-pin eq u ivalent to the in d u stry sta n d ard DAC85 and DA C87 first introduced by B urr-B row n. T heir single-chip design includes the ou tp u t am plifier

TC59WM815BFT

Abstract: 674h AN 7580
Contextual Info: TOSHIBA THLD25N01 B70#75#80 TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 33,554,432-WORD BY 64-BIT DDR SYNCHRONOUS DRAM MODULE DESCRIPTION The THLD25N01B is a 33,554,432-word by 64-bit Double Data Rate synchronous dynamic RAM module consisting of 8 TC59WM815BFT DRAMs on a printed circuit board.

Contextual Info: TOSHIBA THLD25N01 B70#75#80 TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 33,554,432-WORD BY 64-BIT DDR SYNCHRONOUS DRAM MODULE DESCRIPTION The THLD25N01B is a 33,554,432-word by 64-bit Double Data Rate synchronous dynamic RAM module consisting of 8 TC59WM815BFT DRAMs on a printed circuit board.

7MBP25RU2A120

Abstract: marking code C1L 100DC AC2500 ED-4701 H04-004 HCPL-4504 MT5F12959 block diagram of electric cooker
Contextual Info: This m aterial and the inform ation herein is the p ro p e rty o f Fuji E lectric D evice Technology C o., Ltd. They shall be neither reproduced, copied .lent, or disclosed in any w ay w hatsoever for the use of any third party nor used fo r the m anufacturing purposes w ithou t the exp ress w ritte n consent of

Contextual Info: Final Electrical Specifications LTC1343 S o ftw a re -S e le cta b le M u ltip ro to c o l Transceiver u im TECHNOLOGY O c to b e r 1996 F€flTUR€S DCSCRICTIOn • Software-Selectable Transceiver Supports: RS232, RS449, ElA-530, EIA-53Q-A, V.35, V.36, X.21

Q20P010

Abstract: Q20M100 carry look ahead adder Q20080 Q20P025 Q20025 vernier Q20000 Q20004 Q20010
Contextual Info: D EV IC E SP EC IFIC A TIO N LOGIC ARRAYS Q20000 “TURBO” ECL/TTL Q20000 FEATURES Figure 6. Q20080 Die • • • • • • • • • • Up to 18,777 gates, channelless architecture 100 ps equivalent gate delays Low power 0.5-1.0 mW/gate 10K, 10KH, 10OK ECL and mixed ECL/TTL capability

REGULATOR cw 7812

Abstract: 7812A voltage regulator voltage regulator 7808a C7815 7812AC c7805 7809C 78xxK MC7624 7812act
Contextual Info: MOTOROLA MC7800 Series • SEMICONDUCTOR TECHNICAL DATA TH R EE-TER M IN A L POSITIVE FIXED VOLTAGE REGULATORS T H R E E -T E R M IN A L P O S IT IV E V O L T A G E R E G U L A T O R S T h e s e v o lta g e r e g u la t o r s a r e m o n o li t h ic in t e g r a t e d c ir c u it s d e ­