43583 Search Results

A63A

Abstract: 74LSOO
Contextual Info: •Quadruple 2-input Positive AND Gates with Open Collector Outputs IP IN ARRANGEMENT ¡C IR C U IT S C H E M A T IC ^ ) •RECOM M ENDED OPERATING CONDITIONS Symbol min typ max High level output voltage Item VOH - - 5.5 Unit V Low level output current IOL

DIVIDE-BY-256

Abstract: ONU block diagram 74LSOO HD74LS393 a63a
Contextual Info: •D u a l 4-bit Binary Counters This circuit contains eight master-slave flip-flops and ad­ ditional gating to implement tw o individual four-bit counters. The HD74LS393 comprises tw o independent four-bit binary counters each having a clear and a clock input.

74LSOO

Abstract: HD74LS490
Contextual Info: HD74LS490. This c irc u it d itio n a l contains gating to eigh t master-slave im p le m e n t tw o Dual 4 -b it Decade Counters flip -flo p s ind ividu al 4 -b it and ad ­ I BLOCK DIAGRAM K decade counters. Each decade c o u n te r has ind ividu al clo ck, clear, and

74LSOO

Abstract: HD74LS642 Hitachi Scans-001
Contextual Info: ♦ O c ta l Bus Transceivers inverted open-collector outputs This octal bus transceiver is designed fo r asynchronous two-way communication between data buses. The devices transmit data from the A bus to the B bus or from the B bus to the A bus de­ pending upon the level at the direction control (D IR ) input. The

Contextual Info: H D 74A C 168/H D 74A C 169 D escription T he H D 74A C168 and H D 74A C169 are fully syn­ chronous 4-stage u p /d o w n counters. The H D 74A C168 is a BCD decade c o u n te r, the H D 74A C169 is a m odulo-16 binary counter. B oth feature a preset capability for program m able opera­

74LSOO

Contextual Info: •Quadruple 2-input Positive NAND Gates with Open Collector Outputs •C IR C U IT S C H E M A T IC ^ ) BPIN ARRANGEMENT ■RECOMMENDED OPERATING CONDITIONS Symbol min typ max High level output voltage y oh - - 5 .5 Low level output c u rre n t IO L - -

74LSOO

Abstract: CI 2210 HD74LSoop
Contextual Info: •T rip le 3-input Positive NOR Gates • C IR C U IT S C H E M A T IC ^ B P IN ARRANGEMENT ■ELECTRICAL CHARACTERISTICS ( Ta= - 2 0 - +75°C ) Item S ym bol T e s t C o n d itio n s min typ* m ax V lH 2 .0 - - V lL - - 0 .8 U n it Input v o lta g e V

74LSOO

Abstract: 1S2074
Contextual Info: •Q u a d ru p le 2-input Positive N AND Schmitt-triggers •C IR C U IT S C H EM A TIC ^ HPIN ARRANGEMENT ■ELECTRICAL CHARACTERISTICS ( Ta= - 20- + 75”C ) Item Symbol min typ* max Unit Vt + V cc — 5V T e s t Conditions 1.4 1.6 1.9 V Vt ~ V cc — 5V

74LSOO

Abstract: HD74LS367A kl66
Contextual Info: HD74LS367A * Hex Bus Drivers non-inverted data outputs with three-state outputs I PIN ARRANGEMENT I CIRCUIT SCHEMATIC D r i v e r se c tio n (1 / 6 ) C o n t r o l se c tio n Ootpu Control Ci ~ï7 ]vVcc — 1Output Cont roi Ci 'vLLKy L jc t-E I 6 " Y r]D *

ATML U 010

Abstract: ATML H 010 1S2074 400M 74LSOO HD74LS139 OG-16 L400M ATML 010
Contextual Info: H D 74LS139. Dual 2-line-to-4-line Decoders/Demultiplexers IPIN ARRANGEMENT The H D74LS139 comprises two individual two-line-to-fourline decoder in a single package. The active-low enable input can be used as a data line in demultiplexing applications. IBLOCK DIAGRAM

HD74LSoop

Abstract: 1S2074 74LSOO HD74LS195A Hitachi Scans-001 Scans-0014928
Contextual Info: H D 74 L S 19 5A . 4-b¡t Parallel-Access Shift Registers This 4-bit register features parallel inputs, parallel outputs. is loaded into the associated flip-flop and appears at the out­ puts after the positive transition of the clock input. During loading, serial data flow is inhibited. Shifting is accomplished

HN623256FP

Abstract: HN623256P S2074 HN623256
Contextual Info: HN623256P,HN623256FP i ?^ s 32678-word 8-bit Mask Programmable Read Only Memory X The H N 623256P /F P is a mask-programmable byteorganized m em ory designed fo r use in bus-organized systems. The device operates fro m a single pow er supply has co m ­ p a tib ility w ith T T L , and requires no clocks o r refreshing

Contextual Info: • Triple 3-Input N A N D G ate • O u tp u ts Source/Sink 24 m A Pin Assignment T op View D C Characteristics(unless otherwise specified) P aram eter Symbol Condition Unit M ax 1er M axim um Q uiescent Supply C urrent 40 uA = Vcc o r G round, Vcc = 5.5V,

Contextual Info: HITACHI/ LO GIC/A R R A Y S/ M E M TE HD74HC194 DË J 4 4 ^ 2 0 3 001044 3 5 J ~ 92D 1 0 4 4 3 # 4-bit Bidirectional Universal Shift Register This bidirectional sh ift register is designed to incorporate P IN A R R A N G M E N T v irtu a lly all o f the features a system designer may w ant in

Contextual Info: HITACHI/ LOGIC/ARRAYS/MEM Ì2 dÊ J 44^303 0D1D44L. A | - HD74HC195 92D 10446 # 4-bit Parallel-Access Shift Register This shift register feetures parallel inputs, parallel outputs, J-K serial inputs, S hift/L oad control input, and a direct | D T- Hb -O l-ß S

Contextual Info: H I T A C H I / LOGIC/ARRAYS/flEH ^5 4 4 ^ 5 0 3 0010b44 1 92D HD 74H C T240 # 10644 D ]~'SZ-<>7 Octal B u ffers/Line D rivers/L ine Receivers with inverted 3-state outputs PIN ARRANGEMENT The HD74HCT240 is an inverting buffer and has two active low enables (1G and 2G). Each enable independently con­

Contextual Info: HITACHI/ LOGIC/ARRAYS/MEM HD74HCT137 TB DE 4 4 ^ 2 0 3 # 3-to-8-line Decoder/Dem ultiplexer with Address Latch | PIN ARRANGEMENT r-J-a T - , T ¡ ] Vcc B[T - B c^ - C Yi u jy. GL Yi ÏÏ]V i G L^ - A Yfl - C¡ Yi ¡ 2] Yi G i^ - Gi

Contextual Info: Ï Ë J 4 4 cit,2D3 G G 1 D 3 S 7 1 J H I T A C H I / L O G I C / A R R A Y S / N E M "il 92D HD74HC91 üT-ïé-ûf-O 10357 • 8 - bit Shift Register This serial-in, serial-out, 8-bit shift register is composed o f eight R-S master-slave flip-flo ps, inpu t gating, and a clock

Contextual Info: •Quadruple 2-input High-voltage Interface Positive NAND Gates • C IR C U IT SC H EM A TIC O ^ B P IN ARRANGEMENT ■RECOM M ENDED OPERATING CONDITIONS Item S ym bol High lev e l o u tp u t v o lta g e Voh L ow lev el o u tp u t c u r r e n t min ty p

Contextual Info: H I T A C H I / L O G I C / A R R A Y S / M E M ^2 D Ë J 4 MTticüOB OQlQSfl? 4 D T "H611 92D 10587 HD74HC678 16-bit Address Comparator The H D 7 4 H C 6 7 8 address comparator simplifies addressing of | P IN A R R A N G E M E N T m em ory boards and/or other peripheral devices. The four P

Contextual Info: H I T A C H I / L O G I C / A R R A Y S / M E M H D 74H C 374 H D 74H C 534 I S D Ë J M a t a d a 1 5 1 3 fi • Octal D-type Flip-Flops with 3 -state outputs • Octal D-type Flip-Flops (with inverted 3 -state o u tp u ts ) 92D These devices are positive edge triggered flip-flo ps. The d if­

Contextual Info: H D 74A C 165/H D 74A C T 165 # P a r a lle llo a d 8-bit Shift Register Description Pin Assignment This 8-bit serial shift register shifts data from Qa to Q h when clocked, Parallel inputs to each stage are enabled by a low level at the Shift/Load Input.

Contextual Info: "HITACHI/ L O G I C / A R RA YS /M En TS D E I 4 4 ^ 5 0 3 DD Id 3 Mb 4 | .9 2 D HD74HC76 • 10346 D T ~ Ÿ é ~ â 7 -û 7 Dual J-K Flip-Flops with Preset and Clear • PIN ARRANGEMENT Each flip -flo p has independent J, K , preset, clear, and clock

Contextual Info: •Quad 2-Input OR Gate Pin Assignment • O u tp u ts Source/Sink 24m A T op View D C Characteristics (unless otherwise specified) Symbol Parameter Max Icc Maximum Quiescent Supply Current 40 Icc Maximum Quiescent Supply Current 4.0 Unit Condition uA Vin = Vcc or Ground,