CAPACITANCE11 Search Results

Contextual Info: SILICONIX INC 33E I • S2S*|73S 0011=81.3 T ■ .ffSgSfiS T 51 -" DG421/423/425 Low-Power - High-Speed Latchable CMOS Analog Switches FEATURES BENEFITS • Latched Inputs • ± 1 5 Volt Input Range • On-Reslstance < 3 5 Cl • • • • Fast Switching Action t0 N <250 ns •

Contextual Info: Standard Products UT54ACS299 RadHard CMOS 8-bit Universal Shift/Storage Register with Three-State Outputs Preliminary Datasheet November 6, 2006 www.aeroflex.com/radhard LOGIC SYMBOL FEATURES • • • • • • MR Common parallel I/O for reduced pin count

Contextual Info: Standard Products UT54ACTQ16245 RadHard CMOS 16-bit Bidirectional Transceiver, TTL Inputs, and Three-State Outputs Preliminary Datasheet November 2006 www.aeroflex.com/radhard LOGIC SYMBOL FEATURES ‰ 16 non-inverting bidirectional buffers with three-state outputs

Contextual Info: Standard Products UT54ACTQ16374 RadHard CMOS 16-bit D Flip-Flop TTL Inputs, and Three-State Outputs Preliminary Datasheet November 2006 www.aeroflex.com/radhard LOGIC SYMBOL ‰ 16 non-inverting D flip-flops with three-state outputs ‰ Guaranteed simultaneously switching noise level and dynamic threshold performance

Contextual Info: Standard Products UT54ACTQ16374 RadHard CMOS 16-bit D Flip-Flop TTL Inputs, and Three-State Outputs Preliminary Datasheet November 2006 www.aeroflex.com/radhard LOGIC SYMBOL FEATURES ‰ 16 non-inverting D flip-flops with three-state outputs ‰ Guaranteed simultaneously switching noise level and dynamic threshold performance

Contextual Info: Standard Products UT54ACTQ16374 RadHard CMOS 16-bit D Flip-Flop TTL Inputs, and Three-State Outputs Advanced Datasheet September 13, 2006 www.aeroflex.com/radhard FEATURES LOGIC SYMBOL OE1 ‰ 0.6µm Commercial RadHardTM CMOS - Total dose: 100K rad Si - Single Event Latchup immune

sdc 7500 pwm control

Abstract: sdc 7500 MPC5634M MPC5634 mpc5554 emios bosch Knock sensor MPC5554 instruction set npc 1337 LQFP-144 footprint MPC563
Contextual Info: Freescale Semiconductor Data Sheet: Advance Information Document Number: MPC5634M Rev. 2, 12/2008 MPC5634M MPC5634M Microcontroller Data Sheet • Operating Parameters – Fully static operation, 0 MHz - 80 MHz plus 2% frequency modulation - 82 MHz – -40 °C to 150 °C junction temperature operating range

82C54-2-P

Contextual Info: 47E » m Ö235b05 0G321flfl S • SIEG SIEMENS AKTIENGESELLSCHAF Av* "T-S W ^ y $ t\ SAB 82C54 Programmable CMOS Interval Timer SAB 82C54 up to 8 MHz SAB 82C54-2 up to 10 MHz • C om patible w ith all Siemens and m ost other microprocessors • Six program m able counter modes

ML-02-L

Abstract: d1645
Contextual Info: fax id: 5212 CYPRESS C Y 7 C 1 3 8 V /1 4 4 V /0 0 6 V /0 0 7 V PRELIMINARY C Y 7 C 1 3 9 V /1 4 5 V /0 1 6 V /0 1 7 V 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM A u to m atic pow er-dow n Features E xp a n d ab le d ata bus to 16 /18 bits o r m o re using M as ter/

ADSP-21000

Abstract: ADSP-21020 ADSP-21060 ADSP-21062 ADSP-21062L tddg
Contextual Info: a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21062/ADSP-21062L SUMMARY High Performance Signal Processor for Communications, Graphics and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch and Nonintrusive I/O

Contextual Info: ADSP-21060 Industrial SHARC DSP Microcomputer Family ADSP-21060C/ADSP-21060LC ANALOG DEVICES SU M M A R Y High Performance Signal Processor for Com munica­ tions, Graphics, and Im aging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch,

Contextual Info: fax id: 3550 CY7B991V 3.3V RoboClock PRELIMINARY Low Voltage Programmable Skew Clock Buffer Features • All output pair skew <100 ps typical 250 max. • 3.75- to 80-M Hz output operation • User-selectable output functions — Selectable skew to 18 ns

Contextual Info: fax id: 1088 CY7C1333 ADVANCED INFORMATION 64Kx32 Flow-Through SRAM with NoBL Architecture Features Functional Description • S u p p o rts 6 6 -M H z bus o p e ra tio n s w ith zero w ait sta tes— D ata is tra n s ferred on ev e ry clock • In te rn ally se lf-tim e d o u tp u t b u ffe r co n tro l to elim in a te

Contextual Info: ADSP-2106X SHARC DSP Microcomputer Family ANALOG DEVICES ADSP-21061/ADSP-21061L S UM M AR Y High Performance Signal Com puter for Speech, Sound, Graphics and Imaging Applications Super Harvard Architecture Com puter SHARC — Four Independent Buses for Dual Data, Instructions,

JI32

Abstract: SAB-C161JI-LF sab-c161cs-lf bosch ac drive C161CS C161JC C166 J1850 TTL catalog c161jc32
Contextual Info: Da ta S h e e t , V 3 .0 , J a n . 2 0 0 1 C161CS-32R/-L C161JC-32R/-L C161JI-32R/-L 16-Bit Single-Chip Microcontroller Microcontrollers N e v e r s t o p t h i n k i n g . Edition 2001-01 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany

transmitter circuit in GPR

Abstract: marking 5ah 82D series C166 instruction set class A push pull power amplifier XC164CM On Delay Timer Data Sheet single phase ac motor speed control 2200 data sheet c166 C programming
Contextual Info: D a ta S h e e t, V 1 . 2 , M a r c h 20 0 6 XC164CM 16-Bit Single-Chip Microcontroller with C166SV2 Core Microcontrollers Edition 2006-03 Published by Infineon Technologies AG 81726 München, Germany Infineon Technologies AG 2006. All Rights Reserved.

transmitter circuit in GPR

Abstract: xc166 C166 C166SV2 SAF-XC164KM-4F40F SAF-XC164KM-8F20F SAF-XC164KM-8F40F XC164KM TTL catalog
Contextual Info: D a t a S h e et , V 1 . 0 , N o v . 2 0 0 5 XC164KM 1 6 - B i t S i n g l e - C h i p M i c ro c o n t r o ll e r w it h C 1 6 6 S V 2 C o r e M i c r o c o n t r o l l e rs N e v e r s t o p t h i n k i n g . Edition 2005-11 Published by Infineon Technologies AG,

Contextual Info: ADSP-2106X SHARC DSP Microcomputer Family ADSP-21060/ADSP-21060L ANALOG DEVICES SU M M A R Y High Performance Signal Processor for Com munica­ tions, Graphics, and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch,

CY7024

Contextual Info: fax id: 5213 PRELIMINARY CY7C024V/025V/026V CY7C0241V/0251V/036V 3.3V 4K /8K /16K x 16/18 Dual-Port Static RAM Autom atic power-down Expandable data bus to 32/36 bits or more using Mas­ ter/Slave chip select when using more than one device On-chip arbitration logic

Contextual Info: fax id: 5212 ^CYPRESS C Y 7 C 1 3 8 V /1 4 4 V /0 0 6 V /0 0 7 V PRELIMINARY C Y 7 C 1 3 9 V /1 4 5 V /0 1 6 V /0 1 7 V 3.3V 4K/8K/16K/32Kx 8/9 Dual-Port Static RAM A u to m atic p ow er-dow n Features E xp a n d ab le d ata bus to 1 6 /1 8 bits o r m o re using M as ter/

Contextual Info: ^ CYPRESS PREUM INAm CY7C9689 TAXI Compatible HOTLink™ Transceiver Features Second-generation HOTLink™ technology AMD™ AM7968/7969 TAXIchip™ compatible 8-bit 4B/5B or 10-bit 5B/6B NRZI encoded data transport 10-bit or 12-bit NRZI pre-encoded bypass data

INTEL D 2816

Abstract: 2816 rom 8155 intel microprocessor block diagram ROM 2816 2816 memory block diagram of intel 8155 chip Intel 2816 intel 8155 RAM 2816 8155 intel microprocessor architecture
Contextual Info: in te i [p ^ iy iM o iM c w 2816 16K 2K x 8 ELECTRICALLY ERASABLE PROM • HMOS*-E FLOTOX Cell Design ■ Conforms to JEDEC Byte-Wide Family Standard ■ Reliable Floating Gate Technology ■ Microprocessor Compatible Architecture ■ Very Fast Access Time

2164 dynamic ram

Abstract: 2118 intel 2164 RAM Intel 2164 2164 intel 2164 tea 2164 g hidden refresh Intel 2118
Contextual Info: intei' 2164-25 65,536 x 1 BIT DYNAMIC RAM 2164-25 Maximum Access Time ns 250 Read, Write Cycle (ns) 465 Read-Modify-Write Cycle (ns) 530 • Industry Standard 16-pin DIP 128 Refresh Cycles/2 ms RAS-only Refresh ■ HMOS Technology Non-Latched Output is Three-State

8 non inverting buffer

Abstract: MDSC-00039-02
Contextual Info: fS\ Q ualfty S emiconductor, Inc. Low Skew Clock Driver/ Buffer for Desktop PC W i t h 4 DIMMS q s s s is advance INFORMATION FEATURES/BENEFITS DESCRIPTION • • • • • • • The QS5818 is a high speed, low noise 1 - 1 8 non­ inverting buffer designed for SDRAM clock buffer