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    C35B3 Search Results

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    C35B3 Price and Stock

    CTS Corporation

    CTS Corporation 405C35B32M00000

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    Avnet Americas 405C35B32M00000 Tape & Reel 19 Weeks 1,000
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    Mouser Electronics 405C35B32M00000 187
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    Bristol Electronics 405C35B32M00000 1,547
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    Richardson RFPD 405C35B32M00000 1,000
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    CTS Corporation 405C35B33M00000

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    Avnet Americas 405C35B33M00000 Tape & Reel 70 Weeks 1,000
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    Mouser Electronics 405C35B33M00000
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    Richardson RFPD 405C35B33M00000 1,000
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    Avnet Abacus 405C35B33M00000 Tape & Reel 12 Weeks 1,000
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    CTS Corporation 406C35B35M32800

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    Avnet Americas 406C35B35M32800 Tape & Reel 10 Weeks 1,000
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    Mouser Electronics 406C35B35M32800
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    Bristol Electronics 406C35B35M32800 471
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    Richardson RFPD 406C35B35M32800 1,000
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    Avnet Abacus 406C35B35M32800 Tape & Reel 17 Weeks 1,000
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    CTS Corporation 445C35B30M00000

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    Avnet Americas 445C35B30M00000 Tape & Reel 7 Weeks 1,000
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    Mouser Electronics 445C35B30M00000
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    Avnet Abacus 445C35B30M00000 Tape & Reel 17 Weeks 1,000
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    CTS Corporation 406C35B38M88000

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    Avnet Americas 406C35B38M88000 Tape & Reel 10 Weeks 1,000
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    Mouser Electronics 406C35B38M88000
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    Bristol Electronics 406C35B38M88000 1,180
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    Richardson RFPD 406C35B38M88000 1,000
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    Avnet Abacus 406C35B38M88000 Tape & Reel 17 Weeks 1,000
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    C35B3 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    CDAC10

    Contextual Info: ANALOG IP BLOCK CDAC10 - CMOS 10-Bit D/A CONVERTER DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The CDAC10 is a 10-bit high-resolution high-speed CMOS digital-to-analog converter (DAC). The CDAC10 uses a segmented current steering architecture combined with a simple and fast decoding logic to achieve a very high


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    cdac1010-bitc35b3680pf+1330pf PDF

    lvds standard

    Abstract: LVDS_RX SOIC28 MA1014
    Contextual Info: ANALOG IP BLOCK LVDS_RX - CMOS LVDS Receiver DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The LVDS_RX is a differential line receiver designed for applications requiring high data rates. The device supports data rates up to 622Mb/s (311 MHz). The LVDS_RX accepts (350mV) differential input signals and


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    c35b3622mb/s350mv08mm2+4lvds standardlvds_rxsoic28ma1014 PDF

    SCADC10

    Contextual Info: ANALOG IP BLOCK SCADC10 - CMOS 10-Bit A/D CONVERTER DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The SCADC10 is a complete analog to digital converter cell which operates from a single supply. It performs sampling, analog-to-digital conversion, generating a


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    scadc1010-bitc35b3500ks/s+316mm2300khzths3001 PDF

    F100K

    Abstract: SOIC28 transmitter 446 mhz Analog Delay Lines
    Contextual Info: ANALOG IP BLOCK PECL_TX - CMOS PECL Transmitter PROCESS C35B3 0.35um DATA SHEET DESCRIPTION The PECL_TX is a differential 3.3 V PECL transmitter featuring a transmission speed of 622 Mb/s with standard F100K levels (referred to the positive supply). Unlike other


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    c35b3f100ksoic28transmitter 446 mhz+1analog delay lines PDF

    ADC1220

    Abstract: MS 1117 ADC EN16 AD711 AD8138
    Contextual Info: ANALOG IP BLOCK ADC1220 - CMOS 12-Bit Pipelined A/D CONVERTER DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The ADC1220 is a high-speed pipeline ADC core cell achieving sampling rates up to 20 MS/s. A S/H circuit is built-in to provide low jitter noise and a fully differential


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    adc122012-bitc35b3ad8138+3ms 1117 adcen16ad711 PDF

    AD711

    Abstract: THS3001 DIN 3015
    Contextual Info: ANALOG IP BLOCK FLASH6 - CMOS 6-Bit FLASH A/D CONVERTER DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The FLASH6 is a complete analog to digital converter cell which operates from a single supply. It performs sampling, analog-to-digital conversion, generating a


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    c35b3100ms/s32mhzths3001+2ad711din 3015 PDF

    F100K

    Abstract: SOIC28
    Contextual Info: ANALOG IP BLOCK PECL_RX - CMOS PECL Receiver PROCESS C35B3 0.35um FEATURES ! PECL_RX area: 0.1 mm2, ! size: x = 300 µm y = 340 µm PERXBIAS ! 3.3 V ±10% supply voltage ! 622 Mb/s transmission speed size: x = 382 µm y = 375 µm ! 1 ns max. propagation delay


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    c35b3f100ksoic28 PDF

    ADC1020

    Abstract: THS3001 AD1020 AD711 K4103
    Contextual Info: ANALOG IP BLOCK ADC1020 - CMOS 10-Bit Pipelined A/D CONVERTER DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The AD1020 is a high-speed pipeline ADC core cell achieving sampling rates up to 20 MS/s. A S/H circuit is built-in to provide low jitter noise and an optional singleended to fully differential conversion. The reference


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    adc102010-bitc35b3ad1020+557mm212mhzths3001ad711k4103 PDF

    th 2047.5

    Abstract: CDAC12
    Contextual Info: ANALOG IP BLOCK CDAC12 - CMOS 12-Bit D/A CONVERTER DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The CDAC12 is a 12-bit high-resolution high-speed CMOS digital-toanalog converter (DAC). The CDAC12 uses a segmented current steering architecture combined with a simple and fast decoding logic to achieve a very high


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    cdac1212-bitc35b3680pf+2330pfth 2047.5 PDF

    APRIO200P

    Contextual Info: ANALOG IP BLOCK LVDS_RX - CMOS LVDS Receiver DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The LVDS_RX is a differential line receiver designed for applications requiring high data rates. The device supports data rates up to 1Gb/s (500MHz). The LVDS_RX accepts (350mV) differential input signals and


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    c35b3500mhz350mvaprio200p PDF

    AD711

    Abstract: SCADC12
    Contextual Info: ANALOG IP BLOCK SCADC12 - CMOS 12-Bit 4 Channel, Autocalibrating A/D CONVERTER PROCESS DESCRIPTION C35B3 0.35um The SCADC 12 is a complete analog to digital converter cell which operates from a single supply. It performs sampling, analog-to-digital conversion, generating a


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    scadc1212-bitc35b3500khz+4500ks/s300khzths3001ad711 PDF

    LVDS_RX

    Abstract: SOIC28 receiver LVDS_rx LVDS_TX backs
    Contextual Info: ANALOG IP BLOCK LVDS_TX - CMOS LVDS Transmitter DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The LVDS_TX is a differential line driver designed for applications requiring high data rates. The device supports data rates up to 622Mb/s (311 MHz). The LVDS_TX accepts CMOS input levels and translates


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    c35b3622mb/s350mvlvds_rx+4soic28receiver lvds_rxlvds_txbacks PDF

    efp2

    Abstract: AD711 SCADC12F THS3001
    Contextual Info: ANALOG IP BLOCK SCADC12F - CMOS 12-Bit A/D CONVERTER DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The SCADC12F is a complete analog to digital converter cell which operates from a single supply. It performs sampling, analog-to-digital conversion, generating a true 12 bit value in parallel form. The


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    scadc12f12-bitc35b383mm2+3ths3001efp2ad711 PDF

    140U

    Abstract: lvds_tx
    Contextual Info: ANALOG IP BLOCK LVDS_RX - CMOS LVDS Receiver DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The LVDS_RX is a differential line receiver designed for applications requiring high data rates. The device supports data rates up to 1Gb/s (500MHz). The LVDS_RX accepts (350mV) differential input signals and


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    c35b3500mhz350mv140u+1lvds_tx PDF

    C3953

    Contextual Info: 1 1111111111111 111111 1 1111111111111 1 1111111111111 1 1111111111111 1 1 812345678889ABACDEFA8D9 8 888 88888888 88 88888888 8 8 A8C AB8C8 3DE"#$%&'8 ! !8 26*8)98CC8"#$8AABA9 2+,(-3,2(+.


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    8889abacdefa1234567812345678493a58bc3d19e3f3de14e31232775b9+714b54e17a58bcd19e33614b545775b92-14b54e1732984c3953 PDF