BWF CS 30 Search Results

K7N167245A

Abstract: K7N167249A 326J
Contextual Info: Preliminary 256Kx72 Pipelined NtRAMTM K7N167245A Document Title 256Kx72-Bit Pipelined NtRAM TM Revision History Rev. No. 0.0 0.1 0.2 0.3 History Draft Date Remark 1. Initial document. 1. Add JTAG Scan Order 1. Upate DC characteristics icc,isb 1. Speed bin merge.

tc-l 11w

Abstract: K7N167245A K7N167249A
Contextual Info: Preliminary 256Kx72 Pipelined NtRAMTM K7N167245A Document Title 256Kx72-Bit Pipelined NtRAM TM Revision History Rev. No. 0.0 0.1 0.2 0.3 History Draft Date Remark 1. Initial document. 1. Add JTAG Scan Order 1. Upate DC characteristics icc,isb 1. Speed bin merge.

Contextual Info: White Electronic Designs 256Kx72 Synchronous Pipeline SRAM WEDPY256K72V-XBX Preliminary* FEATURES DESCRIPTION n Fast clock speed: 100, 133, 150, 166 and 200* MHz The WEDPY256K72V-XBX employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS

CS22

Abstract: dq35j fast sram 100mhz CS11 CS21 WEDPY256K72V-XBX DQ9-17
Contextual Info: WEDPY256K72V-XBX 256Kx72 Synchronous Pipeline SRAM Preliminary* FEATURES DESCRIPTION ! Fast clock speed: 100, 133, 150, 166 and 200* MHz The WEDPY256K72V-XBX employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. The 16Mb Synchronous SRAMs integrate two 256K

K7N327245M

Abstract: K7N327249M
Contextual Info: Preliminary 512Kx72 Pipelined NtRAMTM K7N327245M Document Title 512Kx72-Bit Pipelined NtRAM TM Revision History Rev. No. 0.0 0.1 History Draft Date Remark 1. Initial document. 1. Speed bin merge. From K7N327249M to K7N327245M 2. AC parameter change. tOH min /tLZC(min) from 0.8 to 1.5 at -25

dq35j

Abstract: CS11 CS21 CS22 WEDPY256K72V-XBX
Contextual Info: White Electronic Designs WEDPY256K72V-XBX 256Kx72 Synchronous Pipeline SRAM DESCRIPTION FEATURES The WEDPY256K72V-XBX employs high-speed, lowpower CMOS designs that are fabricated using an advanced CMOS process. The 16Mb Synchronous SRAMs integrate two 256K x 36 SRAMs into a single

Contextual Info: Preliminary 256Kx72 Pipelined NtRAMTM K7N167245A Document Title 256Kx72-Bit Pipelined NtRAMTM Revision History History Draft Date Remark 0.0 1. Initial document. April. 21. 2001 Preliminary 0.1 1. Add JTAG Scan Order May. 10. 2001 Preliminary Rev. No. The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to c hange the

Contextual Info: WEDPZ512K72S-XBX 512K x 72 Synchronous Pipeline Burst ZBL SRAM *PRELIMINARY FEATURES DESCRIPTION ! Fast clock speed: 150, 133, and 100MHz The WEDC SyncBurst - SRAM employs high-speed, lowpower CMOS design that is fabricated using an advanced CMOS process. WEDC’s 32Mb SyncBurst SRAMs integrate

Contextual Info: Preliminary 256Kx72 Pipelined NtRAMTM K7N167249A Document Title 256Kx72-Bit Pipelined NtRAMTM Revision History History Draft Date Remark 0.0 1. Initial document. April. 21. 2001 Preliminary 0.1 1. Add JTAG Scan Order May. 10. 2001 Preliminary Rev. No. The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to c hange the

K7N167249A

Contextual Info: Preliminary 256Kx72 Pipelined NtRAMTM K7N167249A Document Title 256Kx72-Bit Pipelined NtRAMTM Revision History Rev. No. 0.0 0.1 0.2 History Draft Date Remark 1. Initial document. 1. Add JTAG Scan Order 1. Upate DC characteristics icc,isb April. 21. 2001 May. 10. 2001

dq35j

Abstract: CS11 CS21 CS22 WEDPY256K72V-XBX
Contextual Info: White Electronic Designs WEDPY256K72V-XBX 256Kx72 Synchronous Pipeline SRAM DESCRIPTION FEATURES The WEDPY256K72V-XBX employs high-speed, lowpower CMOS designs that are fabricated using an advanced CMOS process. The 16Mb Synchronous SRAMs integrate two 256K x 36 SRAMs into a single

cs113

Abstract: WEDPZ512K72S-XBX CS10 CS11 CS20 CS21
Contextual Info: White Electronic Designs WEDPZ512K72S-XBX PRELIMINARY* 512K x 72 SYNCHRONOUS PIPELINE BURST ZBL SRAM FEATURES Fast clock speed: 150, 133, and 100MHz Fast access times: 3.8ns, 4.2ns, and 5.0ns Fast OE# access times: 3.8ns, 4.2ns, and 5.0ns High performance 3-1-1-1 access rate

Contextual Info: WEDPY256K72V-XBX 256Kx72 Synchronous Pipeline SRAM FEATURES DESCRIPTION  Fast clock speed: 100, 133, 150, 166 and 200* MHz The WEDPY256K72V-XBX employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. The 16Mb Synchronous SRAMs integrate two 256K x 36 SRAMs

Contextual Info: WEDPY256K72V-XBX 256Kx72 Synchronous Pipeline SRAM FEATURES DESCRIPTION  Fast clock speed: 100, 133, 150, 166 and 200* MHz The WEDPY256K72V-XBX employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. The 16Mb Synchronous SRAMs integrate two 256K x 36 SRAMs

av339

Abstract: Bf b9 IS61NVVP51236-200B IS61NVVP25672 IS61NVVP25672-200B IS61NVVP25672-250B IS61NVVP51236
Contextual Info: IS61NVVP25672 IS61NVVP51236 ISSI 256K x 72 and 512K x 36, 18Mb PIPELINE 'NO WAIT' STATE BUS SRAM ADVANCE INFORMATION JULY 2002 FEATURES DESCRIPTION • 100 percent bus utilization The 16 Meg 'NVVP' product family feature high-speed, low-power synchronous static RAMs designed to provide

Contextual Info: W2Z512K72SJ White Electronic Designs 36Mb, 512K x 72 Synchronous Pipeline Burst NBL SRAM Advanced* FEATURES DESCRIPTION n n n n n n n The WEDC SyncBurst - SRAM family employs highspeed, low-power CMOS designs that are fabricated using an advanced CMOS process. WEDC’s 72Mb

W2Z1M72SJ

Contextual Info: W2Z1M72SJ 72Mb, 1Mx72 Synchronous Pipeline Burst NBL SRAM Preliminary* FEATURES DESCRIPTION n n n n n n n The WEDC SyncBurst - SRAM family employs highspeed, low-power CMOS designs that are fabricated using an advanced CMOS process. WEDC’s 72Mb SyncBurst SRAMs integrate two 1Mx36 SRAMs into a

Contextual Info: W2Z1M72SJ White Electronic Designs 72Mb, 1M x 72 Synchronous Pipeline Burst NBL SRAM Advanced* FEATURES DESCRIPTION n n n n n n n The WEDC SyncBurst - SRAM family employs highspeed, low-power CMOS designs that are fabricated using an advanced CMOS process. WEDC’s 72Mb

W2Z512K72SJ

Contextual Info: W2Z512K72SJ 36Mb, 512Kx72 Synchronous Pipeline Burst NBL SRAM Preliminary* FEATURES DESCRIPTION n Fast clock speed: 225, 200, 166 and 150MHz The WEDC SyncBurst - SRAM family employs highspeed, low-power CMOS designs that are fabricated using an advanced CMOS process. WEDC’s 72Mb

Contextual Info: Preliminary 512Kx72 Pipelined NtRAM TM K7N327245M Document Title 512Kx72-Bit Pipelined NtRAMTM Revision History History Draft Date Remark 0.0 0.1 1. Initial document. 1. Speed bin merge. From K7N327249M to K7N327245M 2. AC parameter change. tOH min /tLZC(min) from 0.8 to 1.5 at -25

K7N167245A

Abstract: K7N167249A
Contextual Info: 256Kx72 Pipelined NtRAM TM K7N167245A Document Title 256Kx72-Bit Pipelined NtRAMTM Revision History History Draft Date Remark 0.0 0.1 0.2 0.3 1. Initial document. 1. Add JTAG Scan Order 1. Update DC characteristics icc,isb 1. Speed bin merge. From K7N167249A to K7N167245A.

NtRAM

Abstract: K7N327245M K7N327249M
Contextual Info: Preliminary 512Kx72 Pipelined NtRAM TM K7N327245M Document Title 512Kx72-Bit Pipelined NtRAMTM Revision History History Draft Date Remark 0.0 1. Initial document. May. 10. 2001 Advance 0.1 1. Speed bin merge. From K7N327249M to K7N327245M 2. AC parameter change.

Contextual Info: ADVANCE U II^ C a n iM ni — 1 MT3LST3264 P , MT5LST6464(P) 32K, 64K x 64 SYNCHRONOUS SRAM MODULE 32K, 64K x 64 SRAM with TAG RAM 256KB/512KB, 3.3V, FLOW-THROUGH OR PIPELINED SYNCHRONOUS BURST, SECONDARY CACHE MODULES FEATURES PIN ASSIGNMENT (Front View)

Contextual Info: . TOSHIBA 11\ I I TC55V1325FF-8, TC55V1325FF -10, TC55V1325FF -12 TECHNICAL DATA SILICON G A TE CMOS TENTATIVE 32,768 W O R D x 32 BIT Synchronous Pipelined Burst SRAM DESCRIPTION The TC55V1325FF is a 1,048,576 bit synchronous pipelined burst SRAM that is organized as 32,768