CY2SSTU877
Abstract: CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T CY2SSTU877BVXI-32
Contextual Info: CY2SSTU877 PRELIMINARY 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features distributes a differential clock input pair CK, CK# to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT#).
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K 2925
Abstract: F1E6
Contextual Info: CY2SSTU877 PRELIMINARY 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features ential pair of clock outputs Y[0:9], Y#[0:9] and one differential pair of feedback clock outputs (FBOUT, FBOUT#). • Operating frequency: 125 MHz to 500 MHz The input clocks (CK, CK#), the feedback clocks (FBIN,
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DDR533
Abstract: CY2SSTU877BVXI-32 CY2SSTU877 CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T
Contextual Info: CY2SSTU877 1.8V, 500 MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features distributes a differential clock input pair CK, CK# to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT#).
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cy2sstu87710-outputddr533cy2sstu877bvxi-32+2cy2sstu877bvxc-32cy2sstu877bvxc-32t
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CY2SSTU877
Abstract: CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T CY2SSTU877BVXI-32 lz 40 6 pin
Contextual Info: CY2SSTU877 PRELIMINARY 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features distributes a differential clock input pair CK, CK# to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT#).
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ddr5
Abstract: DDR533 BV52A CY2SSTU877 CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T CY2SSTU877BVXI-32 DDR-533 DDRII 52-ball
Contextual Info: CY2SSTU877 1.8V, 500 MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features distributes a differential clock input pair CK, CK# to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT#).
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JEDEC MO 224
Abstract: CY2SSTU877 CY2SSTU877BVC-XX CY2SSTU877BVI-XX CY2SSTU877BVI-XXT CY2SSTU877LFC-XX CY2SSTU877LFC-XXT CY2SSTU877LFI-XX JEDEC pin1 qfn tape
Contextual Info: CY2SSTU877 PRELIMINARY 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features • Operating frequency: 125 MHz to 500 MHz • Supports DDRII SDRAM • Ten differential outputs from one differential input • Spread-Spectrum-compatible • Low jitter cycle-to-cycle : < 40 ps
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cy2sstu877500-mhz10-output52-ball+940-pinjedec mo 224cy2sstu877bvc-xxcy2sstu877bvi-xxcy2sstu877bvi-xxtcy2sstu877lfc-xxcy2sstu877lfc-xxtcy2sstu877lfi-xxjedec pin1 qfn tape
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