Part Number
    Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers
    Manufacturer Search

    CY2SSTU877 Search Results

    CY2SSTU877 Datasheets (21)

    Select Manufacturer
    Part ECAD Model Manufacturer Description Datasheet Type PDF PDF Size Page count
    CY2SSTU877
    		Cypress Semiconductor 1.8V, 500-MHz, 10-Output, JEDEC-Compliant Zero Delay Buffer Original PDF 218.36KB 9
    CY2SSTU877
    		Spectra Linear 1.8V, 500MHz 10-Output JEDEC-Compliant Zero Delay Buffer Original PDF 135.11KB 8
    CY2SSTU877BGXC
    		Cypress Semiconductor 1.8V, 500-MHz, 10-Output, JEDEC-Compliant Zero Delay Buffer Original PDF 218.36KB 9
    CY2SSTU877BVC-XX
    		Cypress Semiconductor 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Original PDF 218.38KB 9
    CY2SSTU877BVI-XX
    		Cypress Semiconductor Logic and Timing Misc: 1.8V: 500-MHz: 10-Output JEDEC-Compliant Zero Original PDF 218.35KB 9
    CY2SSTU877BVI-XXT
    		Cypress Semiconductor Logic and Timing Misc: 1.8V: 500-MHz: 10-Output JEDEC-Compliant Zero Delay Original PDF 218.35KB 9
    CY2SSTU877BVXC-32
    		Cypress Semiconductor 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Original PDF 196.93KB 9
    CY2SSTU877BVXC-32
    		Spectra Linear 1.8V, 500MHz 10-Output JEDEC-Compliant Zero Delay Buffer Original PDF 135.1KB 8
    CY2SSTU877BVXC-32T
    		Cypress Semiconductor 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Original PDF 196.92KB 9
    CY2SSTU877BVXC-32T
    		Spectra Linear 1.8V, 500MHz 10-Output JEDEC-Compliant Zero Delay Buffer Original PDF 135.1KB 8
    CY2SSTU877BVXC-XX
    		Cypress Semiconductor Logic and Timing Misc: 1.8V: 500-MHz: 10-Output JEDEC-Compliant Zero Original PDF 218.35KB 9
    CY2SSTU877BVXC-XXT
    		Cypress Semiconductor Logic and Timing Misc: 1.8V: 500-MHz: 10-Output JEDEC-Compliant Zero Delay Original PDF 218.35KB 9
    CY2SSTU877BVXI-32
    		Spectra Linear 1.8V, 500MHz 10-Output JEDEC-Compliant Zero Delay Buffer Original PDF 135.11KB 8
    CY2SSTU877BVXI-XXT
    		Cypress Semiconductor Logic and Timing Misc: 1.8V: 500-MHz: 10-Output JEDEC-Compliant Zero Delay Original PDF 218.35KB 9
    CY2SSTU877LFC-XX
    		Cypress Semiconductor 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Original PDF 218.39KB 9
    CY2SSTU877LFC-XXT
    		Cypress Semiconductor 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Original PDF 218.39KB 9
    CY2SSTU877LFI-XX
    		Cypress Semiconductor Logic and Timing Misc: 1.8V: 500-MHz: 10-Output JEDEC-Compliant Zero Original PDF 218.35KB 9
    CY2SSTU877LFXC-XX
    		Cypress Semiconductor Logic and Timing Misc: 1.8V: 500-MHz: 10-Output JEDEC-Compliant Zero Original PDF 218.35KB 9
    CY2SSTU877LFXC-XXT
    		Cypress Semiconductor Logic and Timing Misc: 1.8V: 500-MHz: 10-Output JEDEC-Compliant Zero Delay Original PDF 218.35KB 9
    CY2SSTU877LFXI-XX
    		Cypress Semiconductor Logic and Timing Misc: 1.8V: 500-MHz: 10-Output JEDEC-Compliant Zero Original PDF 218.35KB 9

    CY2SSTU877 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    CY2SSTU877

    Abstract: CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T CY2SSTU877BVXI-32
    Contextual Info: CY2SSTU877 PRELIMINARY 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features distributes a differential clock input pair CK, CK# to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT#).


    Original     		cy2sstu877500-mhz10-outputcy2sstu877bvxc-32+2cy2sstu877bvxc-32tcy2sstu877bvxi-32 PDF

    K 2925

    Abstract: F1E6
    Contextual Info: CY2SSTU877 PRELIMINARY 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features ential pair of clock outputs Y[0:9], Y#[0:9] and one differential pair of feedback clock outputs (FBOUT, FBOUT#). • Operating frequency: 125 MHz to 500 MHz The input clocks (CK, CK#), the feedback clocks (FBIN,


    Original     		cy2sstu877500-mhz10-output52-ball+2k 2925f1e6 PDF

    DDR533

    Abstract: CY2SSTU877BVXI-32 CY2SSTU877 CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T
    Contextual Info: CY2SSTU877 1.8V, 500 MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features distributes a differential clock input pair CK, CK# to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT#).


    Original     		cy2sstu87710-outputddr533cy2sstu877bvxi-32+2cy2sstu877bvxc-32cy2sstu877bvxc-32t PDF

    CY2SSTU877

    Contextual Info: ADVANCE INFORMATION CY2SSTU877 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features • • • • • • • • • • Functional Description Operating frequency: 125 MHz to 500 MHz Supports DDRII SDRAM Ten differential outputs from one differential input


    Original     		cy2sstu877500-mhz10-output52-ball+140-pin PDF

    CY2SSTU877

    Abstract: CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T CY2SSTU877BVXI-32 lz 40 6 pin
    Contextual Info: CY2SSTU877 PRELIMINARY 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features distributes a differential clock input pair CK, CK# to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT#).


    Original     		cy2sstu877500-mhz10-outputcy2sstu877bvxc-32+3cy2sstu877bvxc-32tcy2sstu877bvxi-32lz 40 6 pin PDF

    ddr5

    Abstract: DDR533 BV52A CY2SSTU877 CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T CY2SSTU877BVXI-32 DDR-533 DDRII 52-ball
    Contextual Info: CY2SSTU877 1.8V, 500 MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features distributes a differential clock input pair CK, CK# to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT#).


    Original     		cy2sstu87710-outputddr5ddr533+7bv52acy2sstu877bvxc-32cy2sstu877bvxc-32tcy2sstu877bvxi-32ddr-533ddrii52-ball PDF

    JEDEC MO 224

    Abstract: CY2SSTU877 CY2SSTU877BVC-XX CY2SSTU877BVI-XX CY2SSTU877BVI-XXT CY2SSTU877LFC-XX CY2SSTU877LFC-XXT CY2SSTU877LFI-XX JEDEC pin1 qfn tape
    Contextual Info: CY2SSTU877 PRELIMINARY 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features • Operating frequency: 125 MHz to 500 MHz • Supports DDRII SDRAM • Ten differential outputs from one differential input • Spread-Spectrum-compatible • Low jitter cycle-to-cycle : < 40 ps


    Original     		cy2sstu877500-mhz10-output52-ball+940-pinjedec mo 224cy2sstu877bvc-xxcy2sstu877bvi-xxcy2sstu877bvi-xxtcy2sstu877lfc-xxcy2sstu877lfc-xxtcy2sstu877lfi-xxjedec pin1 qfn tape PDF

    INSSTE32882

    Abstract: maxim dallas 2501 P16CV SY100EL16 SN65MLVD201 SN65EPT22 INCU877 INCUA877 ttl crystal oscillator using 7404 P16CV857B
    Contextual Info: Clocks and Timing Guide www.ti.com/clocks 2Q 2009 2 Clocks and Timing Guide ➔ Clocks and Timing Selection Tree Clocks by Function Clock Distribution Non- PLL Fanout Buffers PLL Buffers RF Synthesizers Clock Generation General Purpose Generator/Synthesizer


    Original     		insste32882maxim dallas 2501p16cvsy100el16+6sn65mlvd201sn65ept22incu877incua877ttl crystal oscillator using 7404p16cv857b PDF

    INSSTE32882

    Abstract: maxim dallas 2501 insstua32866 INSSTU32864 INSSTU32866 ttl crystal oscillator using CIRCUIT DIAGRAM INCUA877 ps 2501 dallas GSM home automation block diagram INCU877
    Contextual Info: Clocks and Timing Guide www.ti.com/clocks 2Q 2009 2 Clocks and Timing Guide ➔ Clocks and Timing Selection Tree Clocks by Function Clock Distribution Non- PLL Fanout Buffers PLL Buffers RF Synthesizers Clock Generation General Purpose Generator/Synthesizer


    Original     		insste32882maxim dallas 2501insstua32866insstu32864+6insstu32866ttl crystal oscillator using circuit diagramincua877ps 2501 dallasgsm home automation block diagramincu877 PDF