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    CY2SSTU877 Search Results

    CY2SSTU877 Datasheets (21)

    Part ECAD Model Manufacturer Description Datasheet Type PDF PDF Size Page count
    CY2SSTU877
    		Cypress Semiconductor 1.8V, 500-MHz, 10-Output, JEDEC-Compliant Zero Delay Buffer Original PDF 218.36KB 9
    CY2SSTU877
    		Spectra Linear 1.8V, 500MHz 10-Output JEDEC-Compliant Zero Delay Buffer Original PDF 135.11KB 8
    CY2SSTU877BGXC
    		Cypress Semiconductor 1.8V, 500-MHz, 10-Output, JEDEC-Compliant Zero Delay Buffer Original PDF 218.36KB 9
    CY2SSTU877BVC-XX
    		Cypress Semiconductor 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Original PDF 218.38KB 9
    CY2SSTU877BVI-XX
    		Cypress Semiconductor Logic and Timing Misc: 1.8V: 500-MHz: 10-Output JEDEC-Compliant Zero Original PDF 218.35KB 9
    CY2SSTU877BVI-XXT
    		Cypress Semiconductor Logic and Timing Misc: 1.8V: 500-MHz: 10-Output JEDEC-Compliant Zero Delay Original PDF 218.35KB 9
    CY2SSTU877BVXC-32
    		Cypress Semiconductor 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Original PDF 196.93KB 9
    CY2SSTU877BVXC-32
    		Spectra Linear 1.8V, 500MHz 10-Output JEDEC-Compliant Zero Delay Buffer Original PDF 135.1KB 8
    CY2SSTU877BVXC-32T
    		Cypress Semiconductor 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Original PDF 196.92KB 9
    CY2SSTU877BVXC-32T
    		Spectra Linear 1.8V, 500MHz 10-Output JEDEC-Compliant Zero Delay Buffer Original PDF 135.1KB 8
    CY2SSTU877BVXC-XX
    		Cypress Semiconductor Logic and Timing Misc: 1.8V: 500-MHz: 10-Output JEDEC-Compliant Zero Original PDF 218.35KB 9
    CY2SSTU877BVXC-XXT
    		Cypress Semiconductor Logic and Timing Misc: 1.8V: 500-MHz: 10-Output JEDEC-Compliant Zero Delay Original PDF 218.35KB 9
    CY2SSTU877BVXI-32
    		Spectra Linear 1.8V, 500MHz 10-Output JEDEC-Compliant Zero Delay Buffer Original PDF 135.11KB 8
    CY2SSTU877BVXI-XXT
    		Cypress Semiconductor Logic and Timing Misc: 1.8V: 500-MHz: 10-Output JEDEC-Compliant Zero Delay Original PDF 218.35KB 9
    CY2SSTU877LFC-XX
    		Cypress Semiconductor 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Original PDF 218.39KB 9
    CY2SSTU877LFC-XXT
    		Cypress Semiconductor 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Original PDF 218.39KB 9
    CY2SSTU877LFI-XX
    		Cypress Semiconductor Logic and Timing Misc: 1.8V: 500-MHz: 10-Output JEDEC-Compliant Zero Original PDF 218.35KB 9
    CY2SSTU877LFXC-XX
    		Cypress Semiconductor Logic and Timing Misc: 1.8V: 500-MHz: 10-Output JEDEC-Compliant Zero Original PDF 218.35KB 9
    CY2SSTU877LFXC-XXT
    		Cypress Semiconductor Logic and Timing Misc: 1.8V: 500-MHz: 10-Output JEDEC-Compliant Zero Delay Original PDF 218.35KB 9
    CY2SSTU877LFXI-XX
    		Cypress Semiconductor Logic and Timing Misc: 1.8V: 500-MHz: 10-Output JEDEC-Compliant Zero Original PDF 218.35KB 9

    CY2SSTU877 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    CY2SSTU877

    Abstract: CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T CY2SSTU877BVXI-32
    Contextual Info: CY2SSTU877 PRELIMINARY 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features distributes a differential clock input pair CK, CK# to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT#).


    Original     		CY2SSTU877 500-MHz, 10-Output CY2SSTU877 CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T CY2SSTU877BVXI-32 PDF

    K 2925

    Abstract: F1E6
    Contextual Info: CY2SSTU877 PRELIMINARY 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features ential pair of clock outputs Y[0:9], Y#[0:9] and one differential pair of feedback clock outputs (FBOUT, FBOUT#). • Operating frequency: 125 MHz to 500 MHz The input clocks (CK, CK#), the feedback clocks (FBIN,


    Original     		CY2SSTU877 500-MHz, 10-Output 52-ball CY2SSTU877 K 2925 F1E6 PDF

    DDR533

    Abstract: CY2SSTU877BVXI-32 CY2SSTU877 CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T
    Contextual Info: CY2SSTU877 1.8V, 500 MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features distributes a differential clock input pair CK, CK# to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT#).


    Original     		CY2SSTU877 10-Output CY2SSTU877 DDR533 CY2SSTU877BVXI-32 CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T PDF

    CY2SSTU877

    Contextual Info: ADVANCE INFORMATION CY2SSTU877 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features • • • • • • • • • • Functional Description Operating frequency: 125 MHz to 500 MHz Supports DDRII SDRAM Ten differential outputs from one differential input


    Original     		CY2SSTU877 500-MHz, 10-Output 52-ball 40-pin CY2SSTU877 PDF

    CY2SSTU877

    Abstract: CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T CY2SSTU877BVXI-32 lz 40 6 pin
    Contextual Info: CY2SSTU877 PRELIMINARY 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features distributes a differential clock input pair CK, CK# to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT#).


    Original     		CY2SSTU877 500-MHz, 10-Output CY2SSTU877 CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T CY2SSTU877BVXI-32 lz 40 6 pin PDF

    ddr5

    Abstract: DDR533 BV52A CY2SSTU877 CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T CY2SSTU877BVXI-32 DDR-533 DDRII 52-ball
    Contextual Info: CY2SSTU877 1.8V, 500 MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features distributes a differential clock input pair CK, CK# to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT#).


    Original     		CY2SSTU877 10-Output CY2SSTU877 ddr5 DDR533 BV52A CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T CY2SSTU877BVXI-32 DDR-533 DDRII 52-ball PDF

    JEDEC MO 224

    Abstract: CY2SSTU877 CY2SSTU877BVC-XX CY2SSTU877BVI-XX CY2SSTU877BVI-XXT CY2SSTU877LFC-XX CY2SSTU877LFC-XXT CY2SSTU877LFI-XX JEDEC pin1 qfn tape
    Contextual Info: CY2SSTU877 PRELIMINARY 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features • Operating frequency: 125 MHz to 500 MHz • Supports DDRII SDRAM • Ten differential outputs from one differential input • Spread-Spectrum-compatible • Low jitter cycle-to-cycle : < 40 ps


    Original     		CY2SSTU877 500-MHz, 10-Output 52-ball 40-pin CY2SSTU877 JEDEC MO 224 CY2SSTU877BVC-XX CY2SSTU877BVI-XX CY2SSTU877BVI-XXT CY2SSTU877LFC-XX CY2SSTU877LFC-XXT CY2SSTU877LFI-XX JEDEC pin1 qfn tape PDF

    INSSTE32882

    Abstract: maxim dallas 2501 P16CV SY100EL16 SN65MLVD201 SN65EPT22 INCU877 INCUA877 ttl crystal oscillator using 7404 P16CV857B
    Contextual Info: Clocks and Timing Guide www.ti.com/clocks 2Q 2009 2 Clocks and Timing Guide ➔ Clocks and Timing Selection Tree Clocks by Function Clock Distribution Non- PLL Fanout Buffers PLL Buffers RF Synthesizers Clock Generation General Purpose Generator/Synthesizer


    Original     		PDF

    INSSTE32882

    Abstract: maxim dallas 2501 insstua32866 INSSTU32864 INSSTU32866 ttl crystal oscillator using CIRCUIT DIAGRAM INCUA877 ps 2501 dallas GSM home automation block diagram INCU877
    Contextual Info: Clocks and Timing Guide www.ti.com/clocks 2Q 2009 2 Clocks and Timing Guide ➔ Clocks and Timing Selection Tree Clocks by Function Clock Distribution Non- PLL Fanout Buffers PLL Buffers RF Synthesizers Clock Generation General Purpose Generator/Synthesizer


    Original     		PDF