BUSY386 Search Results

82c597

Abstract: 83C206 Cyrix 486 dx2 CX486 386DX CY82C597 intel 486 dx4 t324 amd 386 PC MOTHERBOARD diagram cyrix DX2
Contextual Info: PRELIMINARY CY82C597 386/486 Green Chip Set D Features Page mode DRAM controller supports mixture of 256KB/512KB/1MB/2MB/ 4MB/16MB devices D D MicrosoftR APM support 11 event detectors and 5 userĆdefined timers D D 160ĆPin single chip PQFP Supports PC/AT compatible systems

CX486

Abstract: 83C206 82C596 386D taga7 cyrix DX2 Cyrix 486 dx2 OT502 BIOS source code 386 3118D
Contextual Info: p yp: v « *1 X X PRELIMINARY CY82C597 - 386/486 Green Chip Set Features • 60-Pin single chip PQFP • Supports PC/AT compatible systems at 25/33/40/50 • Supports AMD, Cyrix level 1 w rite-back CPU • W rite-Back/W rite-Through cache with 32KB/64KB/128KB/256KB/512KB/1 MB cache size

80387

Abstract: weitek 85C320 85C330 3i bios chip 80386 85C310 cache controller pipeline architecture for 80386 21U9
Contextual Info: SIS 85C310 _ Cache/Memory Controller Rev 1.1 Preliminary FEATURES • 25/33MHz Non-Pipeline Operation • Built-in Direct Mapped Cache Controller for 32K/64K/128K/256K Cache or More

weitek

Abstract: CASIO keyboard 385DX LIM EMS 4.0 82346
Contextual Info: 0 M F @ m Ä ? 0 rc ] 82346 SYSTEM CONTROLLER The 82346 System Controller is highly configurable via software. No hardware jumpers are required. Defaults on reset for the configuration registers mimic the compatibility requirements of the original IBM PC/AT® as

Contextual Info: D M IF ß fM Ä T rD @ M 82346 SYSTEM CONTROLLER The 82346 System Controller is highly configurable via software. No hardware jumpers are required. Defaults on reset for the configuration registers mimic the compatibility requirements of the original IBM PC/AT as

mt3351

Abstract: Cyrix 486 dx2 MT332 cyrix 486 Port70H 18L15 intel 486 dx4 386 MOTHERBOARD 82c597 cx486
Contextual Info: PRELIMINARY CYPRESS Features • 160-Pin single chip PQFP • Supports PC/AT compatible systems at 25/33/40/50 MHz • Supports AMD, Cyrix level 1 write­ back CPU • Write-Back/Write-Through cache with 32KB/64KB/128KB/256KB/512KB/ 1MB cache size • Non-cachable memory range support

T-538

Abstract: K1557 82c311 82C316 i80387 LG variable frequency drive is3 82C811 hp 1502 vga 82c315 82C81
Contextual Info: CS8233 PEAK/386 AT CHIPSet PEAK/386 AT December 1990 P R E L I M I N A R Y v -ir i i r b Copyright Notice Software Copyright 1990, CHIPS and Technologies, Inc. Manual Copyright © 1990, CHIPS and Technologies, Inc. a 11 r t J .1 r v ig U L » d _ v 6U .

amd 386 PC MOTHERBOARD diagram

Abstract: 83C206 diagram cq 60 motherboard cq 60 motherboard Cyrix 486 dx2 CQ940 CY82C597 cx486 cypress 1994 sram zero intel 486 dx4
Contextual Info: 1CY 82C5 97 PRELIMINARY CY82C597 386/486 Green Chip Set Features • 60-Pin single chip PQFP • Supports PC/AT compatible systems at 25/33/40/50 MHz • Supports AMD, Cyrix level 1 write-back CPU • Write-Back/Write-Through cache with 32KB/64KB/128KB/256KB/512KB/1MB cache size

80486 ADDRESSING MODES EXAMPLES

Abstract: WD6000 LDGE weitek 1L-01 ibm technical
Contextual Info: WD6000 INTRODUCTION 1.0 INTRODUCTION 1.1 D E S C R IP T IO N 1.2 As part of the Western Digital Micro Channel compatible chip sets WD6500, WD6400SX, WD6400SX/LP , the WD6000 CPU and Peripheral Control Logic integrated circuit sig­ nificantly facilitates the design and implementation

Headland Technology Product Group

Abstract: headland headland technology 80386 microprocessor pin out diagram GC205 M240-M241 CC182 logical block diagram of 80286 headland 386 SPA21
Contextual Info: II GCK181 Universal PS/2 Chip Set Headland Technology Inc FEATURES d e s c r ip t io n • Universal Micro Channel Com­ patible chip set supporting the Intel 80286,386SX and 80386 to 25 MHz • Designed in 0.9 Micron channel length HCMOS and BiCMOS in Surface Mount Packages

VL82C330

Abstract: VL82C330FC vl82c3 VL82C331 VL82C topcat VL82C386 vlsi topcat VL82C330-FC
Contextual Info: VLSI INFORMATION T e c h n o l o g y , in c . VL82C330 SYSTEM CONTROLLER DESCRIPTION The VL82C330 System Controller is highly configurable via software. No hardware jum pers are required. Defaults on reset for the configuration registers allow the system to boot at the

SiS 386

Abstract: 80387 386 sis weitek 85C330 sis85
Contextual Info: SIS 85C310 _ Cache/Memory Controller Rev 1.1 Preliminary FEATURES • 25/33MHz Non-Pipeline Operation • Built-in Direct Mapped Cache Controller for 32K/64K/128K/256K Cache or More

80486 ADDRESSING MODES EXAMPLES

Abstract: weitek 4167 S12M3 WD6000 weitek 0070H cdse intel 80386dx WD33C93A 80386DX
Contextual Info: WD6000 INTRO DUCTIO N 1.0 INTRODUCTION 1.1 DESCRIPTION 1.2 As part of the Western Digital Micro Channel compatible chip sets WD6500, WD6400SX, W D6400SX/LP , the WD6000 CPU and Peripheral Control Logic integrated circuit sig­ nificantly facilitates the design and implementation

d472 TRANSISTOR

Abstract: transistor d472 74X374 intel 80386dx WD90C30 E472H stp 1016 a872 TRANSISTOR equivalent d472 OC72
Contextual Info: W D8110Æ V INTRODUCTION 1.0 INTRODUCTION The WD811Q/LV System Controllers are designed to provide a high performance, single chip. sys­ tem controller supporting all 80486SX, 80486DX, 80386SX and 80386DX CPUs In AT bus based Desktop/Lapkjpi'Notetoook/Pen-based systems.

HEADLAND ht 18

Abstract: ht321 HT321-D headland technology 486 motherboard HT321-ISA Headland HT-101 headland PTC S M T209 ptc p175 80387 dx dma techniques .and interface and signal
Contextual Info: HEADLAND T E CH NO LOG Y INC MIE D MS M3b77D2 OdGW S Headland 1 ES HT I HTK320 386DX Chip Set Features • 2-chip 80386DX PC/AT compatible solu­ tion • Supports CPU speeds of up to 40MHz • 3167 W eitek and 80387 co-processor sup­ ported • Peripherals supported on local CPU bus

80387 AMD

Contextual Info: WD8110/LV INTRODUCTION 1.0 INTRODUCTION The WD8110/LV System Controllers are designed to provide a high performance, single chip, sys­ tem controller supporting all 80486SX, 80486DX, 80386SX and 80386DX CPUs in AT bus based Desktop/Laptop/Notebook/Pen-based systems.

Contextual Info: ^^B S S S m PRELIMINARY '* CY82C597 C Y PR E SS 386/486 G reen C hipset Features • 160-Pin single chip PQFP • Supports PC/AT compatible systems at 25/33/40/50 MHz • Supports AMD, Cyrix level 1 write­ back CPU • Write-Back/Write-Through cache with