BUFFERED Search Results

Contextual Info: SN74F378 HEX D-TYPE FLIP-FLOP WITH CLOCK ENABLE S D FS 030B - D2932, M ARCH 1987 - REVISED O CTO B ER 1993 Contains Six D-Type Flip-Flops With Single-Rail Outputs Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Buffered Common Enable Input

SN74F564

Contextual Info: SN54F564, SN74F564 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS D 30 34, SEP T EM B ER 1 9 8 7 -R E V IS E D J A N U A R Y 1989 SN 54 F S6 4 . . . J PACKAGE S N 74F564 . . . DW OR N PACKAGE • 3-State Bus-Driving Inverting Outputs • Buffered Control Inputs

Contextual Info: SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR S D A S 2 1 8 A -A P R IL 1982 - REVISED DECEMBER 1994 SN54ALS273 . . . J PACKAGE SN74ALS273. . . DW OR N PACKAGE TOP VIEW Contain Eight Flip-Flops With Single-Rail Outputs Buffered Clock and Direct-Clear inputs

DACC

Contextual Info: TLV5621E LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER _ • • • • • S L A S 1 3 8 -APRIL 1996 2.7-V to 5.5-V Single-Supply Operation • Low Power Consumption Three 8-Bit Voltage Output DACs • Half-Buffered Output • Power-Down Mode

Contextual Info: TM4EP72BPB, TM4EP72BJB, 4194304 BY 72-BIT TM4EP72CPB, TM4EP72CJB 4194304 BY 72-BIT EXTENDED-DATA-OUT BUFFERED DYNAMIC RAM MODULES _ _ • • • • Long Refresh Periods: - TM4EP72CxB: 64 ms 4096 Cycles

Contextual Info: 74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET _ SCAS064A - D3339. JUNE 1989 - REVISED APRIL 1993 D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Fully Buffered to Offer Maximum Isolation

NV11

Abstract: multiplexers 74 LS 151
Contextual Info: SN54157, SN54LS157, SN54LS158. SN54S157, SN54S158, SN74157, SN74LS157, SN74LS158, SN74S157. SN74S15B QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS M AR C H 1974- - Buffered Inputs and O utputs S N 5 41 57 , S N 54LS 157, S N 54S 157. S N 5 4 L S 1 5 8 , S N 5 4 S 1 5 8 . . . J OR W PACKAGE

74273n

Abstract: 74LS273
Contextual Info: TYPES SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR O CTO BER 1976 • Contains Eight Flip-Flops w ith Single-Rail Outputs • Buffered Clock and D irect Clear Inputs . . J PACKAGE S N 7 4 2 7 3 . . . J OR N PACKAGE S N 7 4 L S 2 7 3 . . . D W , J OR N PACKAGE

Contextual Info: SN54ALS112A, SN74ALS112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS199A – APRIL 1982 – REVISED DECEMBER 1994 • SN54ALS112A . . . J PACKAGE SN74ALS112A . . . D OR N PACKAGE TOP VIEW Fully Buffered to Offer Maximum Isolation

Contextual Info: CD74HC4017-Q1 HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008 D D D D D D D Qualified for Automotive Applications Fully Static Operation Buffered Inputs Common Reset Positive Edge Clocking

Contextual Info: CD74AC175 QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR SCHS347 – APRIL 2003 D D D D D D D D D M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage Buffered Inputs Contains Four Flip-Flops With Double-Rail

Contextual Info: TPS51116 www.ti.com SLUS609C – MAY 2004 – REVISED APRIL 2005 COMPLETE DDR AND DDR2 MEMORY POWER SOLUTION SYNCHRONOUS BUCK CONTROLLER, 3-A LDO, BUFFERED REFERENCE FEATURES • • DESCRIPTION Synchronous Buck Controller VDDQ – Wide-Input Voltage Range: 3.0-V to 28-V

Contextual Info: SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS www.ti.com FEATURES • • • • • • • • • • • • • • • Member of the Texas Instruments Widebus Family UBT™ Transceiver Combines D-Type Latches

1ss nec

Contextual Info: PRELIM INARY DATA S H E E T MOS IN TEGRATED CIRCUIT MC-428LFF72 3.3 V OPERATION 8 M-WORD BY 72-BIT DYNAMIC RAM MODULE BUFFERED TYPE, HYPER PAGE MODE EDO Description Th e M C-428LFF72 1« • 6.388,608 words by 72 bits dynam ic RAM m oduli on which 8 pieces of 84 M DRAM :

IW4042BD

Abstract: IW4042BN
Contextual Info: TECHNICAL DATA IW4042B Quad Clocked «D» Latch High-Voltage Silicon-Gate CMOS IW4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p-channel output devices is balanced and all

Contextual Info: SN74ALS112A, SN54ALS112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FUP-FLOPS WITH CLEAR AND PRESET 02661, A PRIL 1982 - REVISED MAY 1986 • Fully Buffered to Offer Maximum Isolation from External Disturbance • Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers,

Contextual Info: DAC161S055 Precision 16-Bit, Buffered Voltage-Output DAC General Description Key Specifications The DAC161S055 is a precision 16-bit, buffered voltage output Digital-to-Analog Converter DAC that operates from a 2.7V to 5.25V supply with a separate I/O supply pin that operates down to 1.7V. The on-chip precision output buffer

Contextual Info: CD54AC32, CD74AC32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCHS343 – MARCH 2003 D D D D D D D CD54AC32 . . . F PACKAGE CD74AC32 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Buffered Inputs

lpddr3

Abstract: lpddr3 controller LPDDR3 layout TPS59116 str 5 q 0765 POWER SUPPLY CIRCUIT IRF7821 IRF7832 SSTL-18 DDR3 layout TI
Contextual Info: TI Information — Selective Disclosure TPS59116 www.ti.com SLUSA57 – NOVEMBER 2010 Complete DDR, DDR2 and DDR3 Memory Power Solution Synchronous Buck Controller, 3-A LDO, Buffered Reference for Embedded Computing Systems Check for Samples: TPS59116 FEATURES

Analog devices branding codes D6B

Abstract: Analog devices branding codes d5a AD5302 AD5312 AD5322 C300 AD5322ARMZ branding d6B
Contextual Info: 2.5 V to 5.5 V, 230 A, Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs AD5302/AD5312/AD5322 FEATURES GENERAL DESCRIPTION AD5302: Two 8-bit buffered DACs in 1 package A version: ±1 LSB INL, B version: ±0.5 LSB INL AD5312: Two 10-bit buffered DACs in 1 package

q11 hbm

Abstract: HEF4040B HEF4040BP HEF4040BT JESD22-A114E
Contextual Info: HEF4040B 12-stage binary ripple counter Rev. 04 — 4 March 2009 Product data sheet 1. General description The HEF4040B is a 12-stage binary ripple counter with a clock input CP , an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The

CD4025BMS

Abstract: CD4000B CD4000BMS CD4001B CD4001BMS CD4002B CD4002BMS CD4025B H3W CERAMIC FLATPACK
Contextual Info: CD4000BMS, CD4001BMS CD4002BMS, CD4025BMS CMOS NOR Gate November 1994 Features Pinouts • High-Voltage Types 20V Rating CD4000BMS TOP VIEW • Propagation Delay Time = 60ns (typ.) at CL = 50pF, VDD = 10V NC 1 14 VDD • Buffered Inputs and Outputs NC 2

HEF4001BP

Abstract: datasheet of HEF4001BP HEF4001* OR HEF4001BT HEF4001B JESD22-A114E MO-001
Contextual Info: HEF4001B Quad 2-input NOR gate Rev. 05 — 27 March 2008 Product data sheet 1. General description The HEF4001B is a quad 2-input NOR gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS

Contextual Info: . IBM13M64734CCA 64M x 72 2-Bank Registered/Buffered SDRAM Module Features • 168-Pin Registered 8-Byte Dual In-Line Memory Module • 64Mx72 Synchronous DRAM DIMM • Performance: -260 Device Latency fCK Clock Frequency tAC Clock Access Time 2 -360 -360 Units