BL P22 Search Results

TISP3210H3SL

Abstract: TISP3250H3SL TISP3350H3SL GR-1089-CORE TISP3070H3 TISP3070H3SL TISP3080H3 TISP3095H3 TISP3115H3SL TISP3125H3SL
Contextual Info: *R oH VE S CO AV R M AI SIO PL LA N IA BL S NT E TISP3070H3SL THRU TISP3115H3SL, TISP3125H3SL THRU TISP3210H3SL, TISP3250H3SL THRU TISP3350H3SL DUAL BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS TISP3xxxH3SL Overvoltage Protector Series TISP3xxxH3SL Overview

Contextual Info: Z86317 CMOS 8-Blî Z8* MCU C ustom er P rcku rem en t Spe o f ic a tio n ^ Z iL O B Z86317 CMOSZ8 8-BrrMCU FEATURES Part Number Z86317 HW KB RAM* (Bytes) 2 124 Speed (MHz) Package (18-Pin) n K) P24-P27 Can be C onfigured as a V oltage D ivider During Input Mode

Contextual Info: S G S- THOMSON 42E D Bl TTETSB? 0034456 4 B ISSTH r z j s g s - h io m s o ^ ^ 7 # » ^ n ^ © I ( L i© ¥ K C Q ( ^ 0 ( g i S T 9 0 R 4 0 ROMLESS HCMOS MCU WITH EEPROM, RAM AND A/D ADVANCE DATA • Single chip microcontroller with 256 bytes of RAM and 256 bytes of Register File with 224

sharp microwave oven 250

Abstract: sharp SM5k1 SM5* sharp SM5K1 42-PIN 48-PIN SHARP SM5 00011110H 4-bit microcomputer piezo electric buzzer
Contextual Info: SM5K1 4-Bit Microcomputer Microcomputer Data Sheet FEATURES PIN CONNECTIONS • CMOS Process 42-PIN SDIP TOP VIEW • RAM Capacity – 64 x 4-bits Data RAM – 16 × 4-bits Display RAM P20 1 42 VDD P21 2 41 P11 P22 3 40 P12 • 51 Instruction Sets P23 4 39

CSG324

Abstract: transistor bl p89 bl p76 transistor transistor bl p85 XC6SLX150T spartan 6 LX150t bl p78 transistor CPG196 CSG484 xc6slx75csg484
Contextual Info: Spartan-6 FPGA Packaging and Pinouts Product Specification UG385 v1.2 February 22, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

spartan 6 LX150

Abstract: SPARTAN 6 UG385 CSG484 CSG225 CSG324 SPARTAN-6 transistor bl p89 spartan 6 LX150t transistor bl p44 Tr u28 212
Contextual Info: Spartan-6 FPGA Packaging and Pinouts Product Specification UG385 v1.3 October 12, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

CORE F5A

Contextual Info: Preliminary Data Sheet August 2000 m i c r o e le c t r o n ic s group Lucent Technologies Bell Labs Innovations ORCA Series 4 Field-Programmable Gate Arrays Programmable Features • High-performance platform design. — 0.13 pm seven-level metal technology.

PT43C

Abstract: PR41C pin diagram of ic 7495 shift register CORE F5A Y 928 K00 064 PT42C 21-INPUT pr46c OR4E10 k72 u2
Contextual Info: Preliminary Data Sheet August 2000 ORCA Series 4 Field-Programmable Gate Arrays Programmable Features • ■ High-performance platform design. — 0.13 µm seven-level metal technology. — Internal performance of >250 MHz four logic levels . — I/O performance of >416 MHz for all user I/Os.

data vision p113

Abstract: 07H07H DATA VISION P118 ln 7805 ln 7805 regulator VLSI Vision IC2 7805 7805 12v to 5v P241H P102
Contextual Info: VV5300 Sensor Integrated CMOS Image Sensor with on-chip ADC. DISTINCTIVE CHARACTERISTICS Standard image format: 160 x 120 • 164 x 124 pixel array • Variable frame rate 2 fps - 60 fps • On-chip 8-bit A/D convertor • 8-bit and 4-bit conversion modes

data vision p113

Abstract: DATA VISION P118 ln 7805 VV6300 S2016A IC3 7805 ir p119 IR P116 48LCC VLSI Vision
Contextual Info: VV6300 Sensor Integrated CMOS Colour Image Sensor with on-chip ADC. Key Features • Standard image format: 160 x 120 • 2 serial data output modes • 164 x 124 Bayer Patern colour pixel array • Automatic exposure and gain controller • Variable frame rate < 0.3 f/s - 60 f/s

Contextual Info: Data Sheet January 3, 2002 ORCA Series 4 FPGAs Introduction • Traditional I/O selections: — LVTTL and LVCMOS 3.3 V, 2.5 V, and 1.8 V I/Os. — Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. — Individually programmable drive capability:

s26 sharp

Abstract: Single Chip Microcomputers musical FREQUENCY DIVIDER 72-PIN QFP060-P-1414 QFP072-P1010 QFP080-P-1420 QFP072 5L1-25 SHARP SM5
Contextual Info: SM5L1/SM5L2/SM5L3 Microcomputer Data Sheet 4-Bit Single Chip Microcomputers FEATURES • ROM capacity: – 2,048 x 8-bits SM5L1 – 3,072 × 8-bits (SM5L2) – 4,096 × 8-bits (SM5L3) • RAM capacity: – 69 × 4-bits, including 21 × 4-bits display RAM

pt36c equivalent

Abstract: transistor pt36c pt36c pt35c transistor pt42c datasheet transistor pt36C PT42C l22c INTEL Core i7 860 128x8 ram
Contextual Info: Data Sheet January 15, 2002 ORCA Series 4 FPGAs Introduction • Traditional I/O selections: — LVTTL and LVCMOS 3.3 V, 2.5 V, and 1.8 V I/Os. — Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. — Individually programmable drive capability:

Contextual Info: ORCA ORLI10G Quad 2.5Gbps, 10Gbps Quad 3.125Gbps, 12.5Gbps Line Interface FPSC August 2004 Data Sheet Introduction The Lattice ORCA Series 4-based ORLI10G FPSC combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORLI10G consists

BL Super p5 sanyo denki

Abstract: l37a ap13.6 diode BL SUPER P5 Sanyo Denki encoder ORLI10G STM-16 TRCV0110G TTRN0110G TTRN0126
Contextual Info: Data Sheet April, 2002 ORCA ORLI10G Quad 2.5 Gbits/s, 10 Gbits/s Line Interface FPSC Introduction Lattice has developed a new ORCA Series 4-based FPSC which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable embedded system-on-chip SoC

l11D

Abstract: Sanyo Denki encoder transistor BC 667 ORLI10G TRCV0110G TTRN0110G
Contextual Info: Preliminary Data Sheet July 2001 ORCA ORLI10G Field-Programmable System Chip 10 Gbits/s Transmit and Receive Line Interface Introduction Agere Systems Inc has developed a new ORCA Series 4 based FPSC, which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series

l28c

Abstract: MPC8260 ORLI10G STM-16 BM68
Contextual Info: ORCA ORLI10G Quad 2.5Gbps, 10Gbps Quad 3.125Gbps, 12.5Gbps Line Interface FPSC January 2004 Data Sheet Introduction Lattice has developed a new ORCA Series 4-based FPSC which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the

Sanyo Denki encoder

Abstract: MPC8260 ORLI10G STM-16 L28a STM-16 chips 1-256 demultiplexer
Contextual Info: ORCA ORLI10G Quad 2.5Gbps, 10Gbps Quad 3.125Gbps, 12.5Gbps Line Interface FPSC January 2005 Data Sheet Introduction The Lattice ORCA Series 4-based ORLI10G FPSC combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORLI10G consists

L16A

Contextual Info: ORCA ORLI10G Quad 2.5Gbps, 10Gbps Quad 3.125Gbps, 12.5Gbps Line Interface FPSC April 2004 Data Sheet Introduction Lattice has developed a new ORCA Series 4-based FPSC which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the

EEPROM 66B

Abstract: rx2b
Contextual Info: ORCA ORLI10G Quad 2.5Gbps, 10Gbps Quad 3.125Gbps, 12.5Gbps Line Interface FPSC September 2002 Data Sheet Introduction Lattice has developed a new ORCA Series 4-based FPSC which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the

Contextual Info: ORCA ORLI10G Quad 2.5Gbps, 10Gbps Quad 3.125Gbps, 12.5Gbps Line Interface FPSC February 2003 Data Sheet Introduction Lattice has developed a new ORCA Series 4-based FPSC which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the

5K324

Abstract: cmos 4 bit counter 30-PIN 32-PIN QFP036-P-1010 5K3-16 SHARP SM5 uA7300 5K34 5K3-12
Contextual Info: SM5K3/SM5K4/SM5K5 Microcomputer Data Sheet 4-Bit Single-Chip Microcomputer FEATURES DESCRIPTION • 2,048 x 8-bits ROM Capacity The SM5K3/5K4/5K5 are CMOS 4-bit single-chip microcomputers incorporating 4-bit parallel processing function, ROM, RAM, 10-bit A/D converter and timer/

30-PIN

Abstract: 32-PIN QFP036-P-1010 SHARP SM5 bm ra 106 p41 pja 09
Contextual Info: SM5K3/SM5K4/SM5K5 4-Bit Single-Chip Microcomputers Controllers With 10-Bit A/D Converter SM5K3/SM5K4 SM5K5 DESCRIPTION The SM5K3/5K4/5K5 are CMOS 4-bit single-chip microcomputers incorporating 4-bit parallel processing function, ROM, RAM, 10-bit A/D converter

transistor pt36c

Abstract: PT18C datasheet transistor pt36C transistor pt42c pt36c pt35c transistor pt31C pt31c PL34C PT36c transistor
Contextual Info: Preliminary Data Sheet December 2000 ORCA Series 4 Field-Programmable Gate Arrays Programmable Features • ■ High-performance platform design. — 0.13 µm seven-level metal technology. — Internal performance of >250 MHz four logic levels . — I/O performance of >416 MHz for all user I/Os.