BCD 74 Search Results

Contextual Info: MITSUBISHI MICROCOMPUTERS 740 Family Reference Programs 4.3 Code Conversion packed BCD → unpacked BCD (1) Description Packed BCD data is converted to unpacked BCD data. (2) Explanation The packed BCD data at zero page RAM address ADDRPT is converted to the unpacked BCD data

Contextual Info: MITSUBISHI MICROCOMPUTERS 740 Family Reference Programs 4.4 Code Conversion unpacked BCD → packed BCD (1) Description Unpacked BCD data is converted to packed BCD data. (2) Explanation The unpacked BCD data at zero page RAM address ADDRPT +1 and ADDRPT are converted to the

74ac160

Abstract: 74act160 MC74ACT160 ACT160 MC74AC160 MC74AC162 MC74ACT162 74AC162 MC74AC160D 74act162
Contextual Info: MC74AC160 MC74ACT160 MC74AC162 MC74ACT162 Synchronous Presettable BCD Decade Counter SYNCHRONOUS PRESETTABLE BCD DECADE COUNTER The MC74AC160/74ACT160 and MC74AC162/74ACT162 are high-speed synchronous decade counters operating in the BCD 8421 sequence. They

74ac160

Contextual Info: g MC74AC160 MC74ACT160 MC74AC162 MC74ACT162 MOTOROLA Synchronous Presettable BCD Decade Counter SYNCHRONOUS PRESETTABLE BCD DECADE COUNTER The MC74AC160/74ACT160 and MC74AC162/74ACT162 are high-speed synchronous decade counters operating in the BCD (8421) sequence. They

Contextual Info: 74LS490 Signetics Counter Dual BCD Decade Ripple Counter Product Specification Logic Products FEATURES • Two BCD decade counters • Asynchronous Master Set set-to-9 • Asynchronous Master Reset (clear) TYPE 74LS490 The '490 is a Dual BCD Decade Ripple

binary bcd conversion

Abstract: SN54184 SN54185A SN74184 SN74185A tb 10 n 6
Contextual Info: TYPES SN54184, SN54185A, SN74184, SN74185A BCD-TO-BINARY AND BINARY-TO-BCD CONVERTERS FEBRUARY 1971 -R E V IS E D DECEMBER 1972 SN54184, SN74184 BCD TO-BINARY CONVERTERS SN54185A, SN74185A BINARY-TO-BCD CONVERTERS S N 54184, S N 5418 5A . . . J OR W PACKAGE

mod02

Abstract: D 9910 b mod01 9910 mod-01 SFT02 mitsubishi 740
Contextual Info: MITSUBISHI MICROCOMPUTERS 740 Family Reference Programs 4.6 Code Conversion BCD → BIN (1) Description 4-byte BCD data is converted to 4-byte BIN data. (2) Explanation The 4-byte BCD data at zero page RAM addresses BCDDAT, BCDDAT +1, BCDDAT +2, and BCDDAT

BCD to Hexadecimal

Abstract: 001C 110E
Contextual Info: APPLICATION NOTE H8/300L Series Conversion from 5-Digit BCD to 2-Byte Hexadecimal BCD Introduction 1. The software BCD converts a 5-digit BCD (binary-coded decimal) number (3 bytes, placed in general-purpose registers) to a 2-byte hexadecimal number and places the result in a general-purpose register.

MC74AC568

Abstract: 74AC162 MC74ACT160
Contextual Info: g MC74AC160 MC74ACT160 MC74AC162 MC74ACT162 M O TO R O LA Product Preview Synchronous Presettable BCD Decade Counter SYNCHRONOUS PRESETTABLE BCD DECADE COUNTER The MC74AC160/74ACT160 and MC74AC162/74ACT162 are high-speed synchron­ ous decade counters operating in the BCD (8421) sequence. They are synchron­

74LS48

Abstract: 74ls48 PIN OUT TTL 74ls48 decoder 74LS48 SN54/74LS48 LS48 motorola 74ls48 LS 74LS48
Contextual Info: M MOTOROLA. SN54/74LS48 BCD TO 7-SEGMENT DECODER The SN54/74LS48 is a BCD to 7-Segment Decoder consisting of NAND gates, input buffers and seven AND-OR-INVERT gates. Seven NAND gates and one driver are connected in pairs to make BCD data and its complement

74LS48

Abstract: 561 7 SEGMENT ttl 74ls48
Contextual Info: M M OTOROLA SN54/74LS48 BCD TO 7-SEGMENT DECODER The SN54/74LS48 is a BCD to 7-Segment Decoder consisting of NAND gates, input buffers and seven AND-OR-INVERT gates. Seven NAND gates and one driver are connected in pairs to make BCD data and its complement

binary bcd conversion

Abstract: 001C 110E
Contextual Info: APPLICATION NOTE H8/300L Super Low Power Series Conversion from 5-Digit BCD to 2-Byte Hexadecimal BCD Introduction The software BCD converts a 5-digit BCD (binary-coded decimal) number (3 bytes, placed in general-purpose registers) to a 2-byte hexadecimal number and places the result in a general-purpose register.

Contextual Info: MM54C48,MM74C48 MM54C48 MM74C48 BCD-to-7 Segment Decoder Literature Number: SNOS335A MM54C48 MM74C48 BCD-to-7 Segment Decoder General Description Features The MM54C48 MM74C48 BCD-to-7 segment decoder is a monolithic complementary MOS CMOS integrated circuit

CD4028B national

Contextual Info: CD4028BC,CD4028BM CD4028BM/CD4028BC BCD-to-Decimal Decoder Literature Number: SNOS363 CD4028BM CD4028BC BCD-to-Decimal Decoder General Description Features The CD4028BM CD4028BC is a BCD-to-decimal or binaryto-octal decoder consisting of 4 inputs decoding logic

74LS192

Abstract: 74LS192 PIN diagram 74LS192 truth table 74LS193 pin data 74ls193 pin diagram TTL 74ls193 74LS193 truth table 74LS192 INTERNAL DIAGRAM 74LS192 table 74LS193
Contextual Info: SN54/74LS192 SN54/74LS193 PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER PRESETTABLE BCD / DECADE UP/ DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/ DOWN COUNTER The SN54/74LS192 is an UP/DOWN BCD Decade 8421 Counter and the SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate

74LS190 APPLICATIONS

Abstract: 74LS191 truth table of 74LS190 74LS190 PIN diagram 74LS190 Pin 74ls191 pin diagram of 74LS191 3 decade counter
Contextual Info: <8> MOTOROLA, SN54/74LS190 SN54/74LS191 PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS PRESETTABLE BCD/DECADE UP/DOWN COUNTERS The SN 54/74LS 190 is a synchronous UP/DOW N BCD Decade 8421 Counter and the SN54/74LS191 is a synchronous U P /D O W N Modulo-16

4511 7-segment display

Abstract: 74HCT Logic Family Specification AO 4511
Contextual Info: -File Number -TechnicalDa CD54/74HC4511 CD54/74HCT4511 1786 High-Speed CMOS Logic 7-SE6MENT OUTPUTS BCD INPUTS n 7 oo-H BCD-to-7 Segment Latch/ Decoder/Drivers fll/gflMlSlblTlflWl Ä

74LS192 truth table

Abstract: 74LS193 truth table 74LS192 PIN diagram 74ls193 74LS192 74LS192 INTERNAL DIAGRAM TTL 74ls193 74LS193 pin data 74LS192 table ttl 74ls192
Contextual Info: SN54/74LS192 SN54/74LS193 PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER PRESETTABLE BCD/ DECADE UP/ DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/ DOWN COUNTER The SN54/74LS192 is an UP/DOWN BCD Decade 8421 Counter and the SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate

SN74184

Abstract: SN74185A SN54184 SN54185A binary to bcd 12 bits bcd binary conversion application note SN5488 SN74185
Contextual Info: CIRCUIT TYPES SN54184, SN54185A, SN74184, SN74185A BCD-TO-BINARY AND BINARY-TO-BCD CONVERTERS SN54184, SN74184 BCD-TO-BINARY CO NVERTERS SN54185A, SN74185A BINARY-TO-BCD CO NVERTERS J O R N D U A L - IN - L IN E O R W F L A T P A C K A G E T O P V IE W lt

Contextual Info: Semiconductor February 1988 CD4028BM/CD4028BC BCD-to-Decimal Decoder General Description Features The CD4028BM/CD4028BC is a BCD-to-decimal or binaryto-octal decoder consisting of 4 inputs, decoding logic gates, and 10 output buffers. A BCD code applied to the 4

74F582

Abstract: bcd arithmetic binary bcd conversion N74F582D N74F582N binary to bcd
Contextual Info: FAST 74F582 4-Bit BCD Arithmetic Logic Unit Product Specification FAST Products FEATURES TYPE The 'F582 input and output logic in­ cludes a C arry/B orrow w hich is generat­ ed internally in the look-ahead mode, allowing BCD arithm etic to be com puted directly. For more than one BCD de­

74LS48

Abstract: 74ls48 PIN OUT decoder 74LS48 TTL 74LS48 74ls48 datasheet 74LS48D LS48 lamptest 561 7 SEGMENT
Contextual Info: SN54/74LS48 BCD TO 7-SEGMENT DECODER The SN54 / 74LS48 is a BCD to 7-Segment Decoder consisting of NAND gates, input buffers and seven AND-OR-INVERT gates. Seven NAND gates and one driver are connected in pairs to make BCD data and its complement available to the seven decoding AND-OR-INVERT gates. The remaining

74185A

Abstract: 74S485 20-BIT-BINARY-TO-BCD 12-BIT-BINARY-TO-BCD 54185A ln214 S485A
Contextual Info: TTL LSI SN54S484A, SN54S485A, SN74S484A, SN74S485A BCD TO BINARY AND BINARY TOBCD CONVERTERS D 2 5 3 4 , JUN E 1 9 7 9 - REVISED FEBRUARY 1 9 8 4 S N 54S 484A , S N 74S 484A . BCD-TO-BINARY CONVERTERS S N 54S 485A , SN 74S 485A BINARY-TO BCD CONVERTERS Significant Savings in Package Count

74LS48

Abstract: decoder 74LS48 74ls48 PIN OUT 74LS48D ttl 74ls48 LS48 74LS48 function table
Contextual Info: SN54/74LS48 BCD TO 7-SEGMENT DECODER The SN54 / 74LS48 is a BCD to 7-Segment Decoder consisting of NAND gates, input buffers and seven AND-OR-INVERT gates. Seven NAND gates and one driver are connected in pairs to make BCD data and its complement available to the seven decoding AND-OR-INVERT gates. The remaining