B5011ES Search Results

54F413DM

Abstract: 74F10 74F413PC J16A N16E
Contextual Info: & National Semiconductor 54F/74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O General Description Features The 'F413 is an expandable fall-through type high-speed First-In First-Out FIFO buffer memory organized as 64 words by four bits. The 4-bit input and output registers rec­

Contextual Info: NATIONAL SEMICOND LOGIC 31E D b501122 0071Q71 2 I 100114 rr\ National ÆjA Semiconductor F100114 Quint Differential Line Receiver General Description The F10Q114 is a monolithic quint differential line receiver with emitter-foilower outputs. An internal reference supply

ns32032

Abstract: tl 451 NS32301 NS32201 NS32082
Contextual Info: NATL SEHICONÎ 6501128 NATL -CUP/UO SEM ICOND, AD DEJ| b S D U S f l 80C '5 5 4 5 7 U P/U C ) DT-5S-3340 ADVANCED INFORMATION NS32301-10/NS32301-15 Timing Control Unit 1.0 General Description 2.0 Features The NS32301 Timing Control Unit (TCU) is a 28 pin device

730N

Contextual Info: National Semiconductor 74F27 Triple 3-Input NOR Gate General Description This device contains three independent gates, each of which performs the logic N OR function. Ordering Code: see section 11 Package Number Commercial Package Description 74F27PC N14A