B0001001 Search Results

LUPA-3000

Abstract: switch Signal LUX L4 LUPA3000 AN57864 CMOS global shutter b1000001 Color Filter Array CFA schematic diagram ip camera
Contextual Info: NOIL1SN3000A LUPA3000: 3 MegaPixel High Speed CMOS Sensor Features • • • • • • • • • • • • • • • • 1696 x 1710 Active Pixels 8 mm x 8 mm Square Pixels 1.2 inch Optical Format Monochrome or Color Digital Output 485 Frames per Second fps Frame Rate

TAG 8926

Abstract: Lpg 899 SDC 2921 TF 6221 HEN LED display 12V+RELAY+1+C/8 pin ic sdc 3733
Contextual Info: MCIMX31 and MCIMX31L Multimedia Applications Processors Reference Manual MCIMX31RM Rev. 1 2/2006 How to Reach Us: USA/Europe/Locations Not Listed: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 480-768-2130

sandisk eMMC 4.41

Abstract: toshiba emmc 4.4 spec SANDISK inand Samsung eMMC 4.41 sandisk emmc 4.5 bcm 4330 programming Guide Sandisk iNAND eMMC toshiba emmc 4.4 linux toshiba emmc 4.4.1 spec sandisk inand extreme emmc
Contextual Info: An addendum for this document is available. See Document ID#: IMX25RMAD. i.MX25 Multimedia Applications Processor Reference Manual Supports i.MX251 MCIMX251 i.MX253 (MCIMX253) i.MX255 (MCIMX255) i.MX257 (MCIMX257) i.MX258 (MCIMX258) IMX25RM Rev. 1 06/2009

LUPA-3000

Abstract: NOIL1SN3000A Color Filter Array CFA an52561
Contextual Info: NOIL1SN3000A LUPA3000: 3 MegaPixel High Speed CMOS Sensor Features • • • • • • • • • • • • • • • • 1696 x 1710 Active Pixels 8 mm x 8 mm Square Pixels 1.2 inch Optical Format Monochrome or Color Digital Output 485 Frames per Second fps Frame Rate

Contextual Info: Agilent HDMP-2689 Quad 2.125/1.0625 GBd Fibre Channel General Purpose SerDes Data Sheet • Source synchronous single data rate clocking of transmit parallel data for 1.0625 GBd serial rate • MII management interface for chip control and status Description

bcm 4330 programming Guide

Abstract: BCM 4334 bcm 4339 bcm 4330 sony cmos sensor imx 172 heart beat sensor using led and ldr philips 432 cnc controller philips 432 cnc digital stopwatch with 4026 cmos auo display HP printer
Contextual Info: MCIMX27 Multimedia Applications Processor Reference Manual MCIMX27RM Rev. 0.3 12/2008 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370

VT6526

Abstract: DM9161A FALC56 errata VT6526A VT6510B DIODE JS4 FALC56 application note FALC56 MPC8122 Oscilloscope USB 200Mhz Schematic
Contextual Info: MSC8122/26ADS Reference Manual MSC8122/26 Application Development System MSC812xADSRM Rev B.01, September 2006 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc.

ARM1136EJ-S

Abstract: MCIMX35 ARM1136ej IMX35RM IMX35RMAD TC58NVG4D TC58NVG4 LPG GAS SENSOR din 74324 emmc spec
Contextual Info: An addendum for this document is available. See Document ID#: IMX35RMAD. i.MX35 MCIMX35 Multimedia Applications Processor Reference Manual Supports i.MX35 (MCIMX35) i.MX351 (MCIMX351) i.MX353 (MCIMX353) i.MX355 (MCIMX355) i.MX356 (MCIMX356) i.MX357 (MCIMX357)

CHN 803

Abstract: NTK ALARM IC AH52 1F
Contextual Info: PHY TC-PMD USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS ADVANCED INFORMATION IDT77155 In teg rated D evice Technology, Inc. KEY FEATURES • Supports up to 4 PHYs for Multi-PHY connections with 2bit address and 8-bit data using UTOPIA 2 protocol.

TXC-07905-MB

Abstract: TXC-07905 OED622 B016H BP85H MSP SNCP h-12-H cu3ah B007H
Contextual Info: OED622 Device Dual STM-4/STM-1 Overhead Terminator, Tributary Processor and Cross-Connect with Integrated E1 Mapper TXC-07905 PRODUCT PREVIEW DATA SHEET DESCRIPTION: ™ The Optimized Edge Device, OED622, is a dual STM-4/STM-1 SDH framer and overhead terminator, virtual

ML605 UCF FILE

Abstract: XAPP1052 asus motherboard virtex-6 ML605 user guide TLP 3616 dell power edge xapp1052 document "Asus P5B-VM" Xilinx Spartan-6 FPGA Kits XBMD
Contextual Info: Application Note: Virtex-6, Virtex-5, Spartan-6 and Spartan-3 FPGA Families Bus Master DMA Performance Demonstration Reference Design for the Xilinx Endpoint PCI Express Solutions XAPP1052 v2.5 December 3, 2009 Summary Author: Jake Wiltgen and John Ayer

Contextual Info: NOIL1SN3000A LUPA3000: 3 MegaPixel High Speed CMOS Sensor Features • • • • • • • • • • • • • • • • 1696 x 1710 Active Pixels 8 mm x 8 mm Square Pixels 1.2 inch Optical Format Monochrome or Color Digital Output 485 Frames per Second fps Frame Rate

CHN 709

Abstract: C2979
Contextual Info: PHY TC-PMD USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS IDT77155 Integrated Device Technology, Inc. KEY FEATURES • One chip ATM User Network Interface for 155.52 Mbps/ 5 1 .84Mbps operating speed. • Full implementation of the SONET/SDH criteria according

hecs 50

Abstract: atm header error checking BIP 109 atm header-error-check multiple bit BIP-8 cmos 4 bit counter STM-1 Physical interface PHY TCA 810 128-PIN GR-253-CORE
Contextual Info: PHY TC-PMD USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS ADVANCED INFORMATION IDT77155 Integrated Device Technology, Inc. KEY FEATURES • One chip ATM User Network Interface for 155.52 Mbps/ 51.84Mbps operating speed. • Full implementation of the SONET/SDH criteria according

asus motherboard

Abstract: design of dma controller using vhdl ML605 UCF FILE TLP 3616 XILINX/SPARTAN 3E STARTER BOARD "Asus P5B-VM" XBMD sp605 virtex-6 ML605 user guide virtex ucf file 6
Contextual Info: Application Note: Virtex-6, Virtex-5, Spartan-6 and Spartan-3 FPGA Families Bus Master DMA Performance Demonstration Reference Design for the Xilinx Endpoint PCI Express Solutions XAPP1052 November 4, 2010 Summary Author: Jake Wiltgen and John Ayer This application note discusses how to design and implement a Bus Master Direct Memory

LUPA-3000

Abstract: 357 opto
Contextual Info: NOIL1SN3000A LUPA3000: 3 MegaPixel High Speed CMOS Sensor Features • • • • • • • • • • • • • • • • 1696 x 1710 Active Pixels 8 mm x 8 mm Square Pixels 1.2 inch Optical Format Monochrome or Color Digital Output 485 Frames per Second fps Frame Rate

STA016

Abstract: STA016T TQFP64 G723-40
Contextual Info: STA016T MPEG 2.5 LAYER III AUDIO DECODER SUPPORTING CD-ROM CAPABILITY & ADPCM PRODUCT PREVIEW • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SINGLE CHIP MPEG LAYER 3 DECODER SUPPORTING: - All features specified for Layer III in ISO/IEC 11172-3 MPEG 1 Audio

Contextual Info: STA016T MPEG 2.5 LAYER III AUDIO DECODER SUPPORTING CD-ROM CAPABILITY & ADPCM PRODUCT PREVIEW • SINGLE CHIP MPEG LAYER 3 DECODER SUPPORTING: - All features specified for Layer III in ISO/IEC 11172-3 MPEG 1 Audio - All features specified for Layer III in ISO/IEC

D 2689

Abstract: n05 marking code A03 AGILENT marking h06 HDMP-2689 HFBR-5720L
Contextual Info: Agilent HDMP-2689 Quad 2.125/1.0625 GBd Fibre Channel General Purpose SerDes Data Sheet • Source synchronous single data rate clocking of transmit parallel data for 1.0625 GBd serial rate • MII management interface for chip control and status Description

pick*up cd*rom

Abstract: CF11 dsp diode B7 MA27 MA28 mpeg2 coder PEH 165 STA016 STA016T TQFP64
Contextual Info: STA016T MPEG 2.5 LAYER III AUDIO DECODER SUPPORTING CD-ROM CAPABILITY & ADPCM PRODUCT PREVIEW SINGLE CHIP MPEG LAYER 3 DECODER SUPPORTING: - All features specified for Layer III in ISO/IEC 11172-3 MPEG 1 Audio - All features specified for Layer III in ISO/IEC

aag2

Abstract: T03 T04 T02 T05 tdc8 AAG2 marking
Contextual Info: Agilent HDMP-2689 Quad 2.125/1.0625 GBd Fibre Channel General Purpose SerDes Data Sheet • Source synchronous single data rate clocking of transmit parallel data for 1.0625 GBd serial rate • MII management interface for chip control and status Description

XAPP1052

Abstract: asus motherboard FPGA based dma controller using vhdl asus motherboard data sheet asus p5b XC5VLX50T-1FFG1136 dell power edge virtex 2 pro XAPP1002 "Asus P5B-VM"
Contextual Info: Application Note: Virtex-5 Family R XAPP1052 v1.1 August 22, 2008 Summary Bus Master DMA Reference Design for the Xilinx Endpoint Block Plus Core for PCI Express Author: Jake Wiltgen This application note discusses how to design and implement a Bus Master Direct Memory

STA016A

Abstract: TQFP64 320kbit PEH SOFTWARE
Contextual Info: STA016A MPEG 2.5 LAYER III AUDIO DECODER SUPPORTING CD-ROM CAPABILITY PRODUCT PREVIEW STA016AASTA016AA 1 • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ FEATURES SINGLE CHIP MPEG LAYER 3 DECODER SUPPORTING: – All features specified for Layer III in ISO/IEC

GR-253-CORE

Abstract: IDT77155 IIDT77155 128-PIN AN-173 hecs 50 3rk1
Contextual Info: IDT77155 PHY TC-PMD USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS Integrated Device Technology, Inc. KEY FEATURES • One chip ATM User Network Interface for 155.52 Mbps/ 51.84Mbps operating speed. • Full implementation of the SONET/SDH criteria according