DS768
Abstract: AMBA AXI4 verilog code axi4-lite and apb protocol AMBA AXI4 AMBA AXI to APB BUS Bridge vhdl code
Contextual Info: LogiCORE IP AXI Interconnect v1.04.a DS768 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Interconnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI
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ds768amba axi4 verilog codeaxi4-lite and apb protocolamba axi4+1amba axi to apb bus bridge vhdl code
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Contextual Info: LogiCORE IP AXI Interconnect v1.06.a DS768 December 18, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Interconnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI
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DS768
Abstract: axi4-lite and apb protocol AMBA AXI to APB BUS Bridge vhdl code AXI4 lite verilog AMBA file write AXI verilog code AMBA AXI dma controller designer user guide
Contextual Info: LogiCORE IP AXI Interconnect v1.06.a DS768 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Interconnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI
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ds768zynqtm-7000axi4-lite and apb protocolamba axi to apb bus bridge vhdl code+3axi4 lite verilogamba file write axi verilog codeamba axi dma controller designer user guide
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axi ethernet lite software example
Abstract: microblaze axi ethernet lite zynq axi ethernet software example microblaze ethernet lite fpga cdma by vhdl examples DS787
Contextual Info: LogiCORE IP AXI Ethernet Lite MAC v1.01.b DS787 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The Advanced Microcontroller Bus Architecture (AMBA ) Advanced eXtensible Interface (AXI) AXI Ethernet Lite MAC (Media Access Controller) is
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ds787axi ethernet lite software examplemicroblaze axi ethernet litezynq axi ethernet software example+2microblaze ethernet litefpga cdma by vhdl examples
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AXI4 lite verilog
Abstract: AMBA AXI verilog code AMBA AXI4 verilog code AXI4 verilog AMBA AXI specifications AMBA AXI4 cdn_axi4_slave_bfm DS824 axi bfm axi wrapper
Contextual Info: AXI Bus Functional Models v2.1 DS824 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The AXI Bus Functional Models BFMs , developed for Xilinx by Cadence Design Systems, support the simulation of customer-designed AXI-based IP. AXI
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ds824axi4 lite verilogamba axi verilog codeamba axi4 verilog code+6axi4 verilogamba axi specificationsamba axi4cdn_axi4_slave_bfmaxi bfmaxi wrapper
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uart 16550
Abstract: XC6SLX16CSG324 AMBA AXI4 XC6SLX16-CSG324 XC6VLX75T-FF784 uart vhdl fpga UART16550 V6 6D XC7V855T National Semiconductor PC16550D UART
Contextual Info: LogiCORE IP AXI UART 16550 v1.01a DS748 June 22, 2011 Product Specification Introduction LogiCORE IP Facts Table The AXI Universal Asynchronous Receiver Transmitter (UART) 16550 connects to the AMBA (Advance Microcontroller Bus Architecture) AXI (Advanced
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ds748pc16550duart 16550xc6slx16csg324+8amba axi4xc6slx16-csg324xc6vlx75t-ff784uart vhdl fpgauart16550v6 6dxc7v855tnational semiconductor pc16550d uart
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state machine axi 3 protocol
Abstract: XPS IIC xilinx vhdl rs232 code axi interconnect xilinx 0X138 ZYNQ-7000
Contextual Info: LogiCORE IP AXI IIC Bus Interface v1.02a DS756 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The AXI IIC Bus Interface connects to the Advanced Microcontroller Bus Architecture (AMBA ) specification’s Advanced eXtensible Interface (AXI)
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ds756state machine axi 3 protocolxps iicxilinx vhdl rs232 code+3axi interconnect xilinx0x138zynq-7000
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XC6SLX45t-fgg484
Abstract: XC6VLX240T-FF1156 awid communication protocol axi wrapper xc6slx45tfgg484 AXI4 verilog TM7000 Datasheet
Contextual Info: LogiCORE IP ChipScope AXI Monitor v3.03.a DS810 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The ChipScope AXI Monitor core is designed to monitor and debug AXI interfaces. The core allows the probing of any signals going from a peripheral to the
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ds810tm-7000xc6slx45t-fgg484xc6vlx240t-ff1156+5awid communication protocolaxi wrapperxc6slx45tfgg484axi4 verilogtm7000 datasheet
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Contextual Info: LogiCORE IP AXI INTC v1.04a DS747 June 19, 2013 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Interrupt Controller (AXI INTC) core receives multiple interrupt inputs from peripheral devices and merges them to a single
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XC6SLX16-CSG324
Abstract: XC6SLX16CSG324 uart 16550 HOLDING UART16550 16550 uart timing XC7K410TFFG676-3
Contextual Info: LogiCORE IP AXI UART 16550 v1.01a DS748 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The AXI Universal Asynchronous Receiver Transmitter (UART) 16550 connects to the AMBA (Advance Microcontroller Bus Architecture) AXI (Advanced
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ds748pc16550dpc165otifyxc6slx16-csg324+6xc6slx16csg324uart 16550holdinguart1655016550 uart timingxc7k410tffg676-3
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Contextual Info: LogiCORE IP AXI INTC v1.03a DS747 October 16, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Interrupt Controller (AXI INTC) core receives multiple interrupt inputs from peripheral devices and merges them to a single
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BP131
Abstract: CL013G arm axi
Contextual Info: PrimeCell Infrastructure AMBA 3 AXI Downsizer BP131 Revision: r0p0 Technical Overview This Technical Overview describes the functionality of the AXI downsizer in the following sections: • Preliminary material on page 2 • About the AXI downsizer on page 4
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Contextual Info: LogiCORE IP AXI Quad Serial Peripheral Interface AXI Quad SPI v2.00a DS843 December 18, 2012 Product Specification Introduction LogiCORE IP Facts The AXI Quad SPI connects the AXI4 interface to those SPI slave devices that support Standard, Dual or Quad
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axi interconnect xilinx
Abstract: axi3
Contextual Info: LogiCORE IP AXI External Slave Connector v1.00.a DS805 January 18, 2012 Product Specification Introduction LogiCORE IP Facts Table AXI External Slave Connector (axi_ext_slave_conn), lets you connect an AXI slave device outside of the embedded system module, using embedded module
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ds805zynqtm-7000axi interconnect xilinxaxi3 |
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xc6vlx130t-ff1156
Abstract: XILINX ipic axi
Contextual Info: LogiCORE IP AXI Serial Peripheral Interface AXI SPI (v1.02.a) DS742 January 18, 2012 Product Specification Introduction LogiCORE IP Facts The AXI Serial Peripheral Interface (SPI) connects to the Advanced eXtensible Interface (AXI4). This core provides a serial interface to SPI devices such as SPI
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ds742m68hc1132-bitxc6vlx130t-ff1156+1xilinx ipic axi
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Xilinx Spartan-6 LX4
Abstract: DS817 spartan6 jtag instruction spartan 6 LX150 fifo generator xilinx spartan state machine axi axi crossbar Xilinx Spartan 6 LX75 icape2 state machine axi 3 protocol
Contextual Info: LogiCORE IP AXI HWICAP v2.02.a DS817 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The Xilinx LogiCORE IP Advanced eXtensible Interface (AXI) HWICAP (Hardware Internal Configuration Access Port) core for the AXI Interface
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ds817zynqtm-7000xilinx spartan-6 lx4spartan6 jtag instruction+7spartan 6 lx150fifo generator xilinx spartanstate machine axiaxi crossbarxilinx spartan 6 lx75icape2state machine axi 3 protocol
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N25Q256
Abstract: WINBOND W25Q80 XC7K325TFFG900 XC6VLX130TFF1156 W25Q64VSFIG XC7K325T W25Q64vs axi4 DS843 W25Q80
Contextual Info: LogiCORE IP AXI Quad Serial Peripheral Interface AXI Quad SPI (v1.00a) DS843 October 19, 2011 Product Specification Introduction LogiCORE IP Facts The AXI Quad Serial Peripheral Interface connects the AXI4 interface to SPI slave devices that support the
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ds843m68hc11n25q256winbond w25q80+7xc7k325tffg900xc6vlx130tff1156w25q64vsfigxc7k325tw25q64vsaxi4w25q80
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XC7K325TFFG900
Abstract: W25Q64VSFIG WINBOND W25Q80 SPARTAN 6 spi numonyx XPS ipic burst axi4 example Quad SPI N25Q256 NUMONYX xilinx spi XC7V285TFFG784-3 XC7K325T-ffg900
Contextual Info: LogiCORE IP AXI Quad Serial Peripheral Interface AXI Quad SPI (v2.00a) DS843 July 25, 2012 Product Specification Introduction LogiCORE IP Facts The AXI Quad SPI connects the AXI4 interface to those SPI slave devices that support Standard, Dual or Quad
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ds843m68hc11zynq-7000xc7k325tffg900+9w25q64vsfigwinbond w25q80spartan 6 spi numonyxxps ipic burst axi4 examplequad spin25q256numonyx xilinx spixc7v285tffg784-3xc7k325t-ffg900
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XC6SLX45t-fgg484
Abstract: XC6VLX240T-FF1156 xc6vlx240tff1156-1 AMBA AXI4 stream specifications XC6VLX240T-FF1156-1 xc6vlx240tff1156 xc6slx45tfgg484 XC6SLX45T kintex 7 AMBA AXI designer user guide
Contextual Info: LogiCORE IP ChipScope AXI Monitor v3.01.a DS810 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The ChipScope AXI Monitor core is designed to monitor and debug AXI interfaces. The core allows the probing of any signals going from a peripheral to the
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ds810xc6slx45t-fgg484xc6vlx240t-ff1156xc6vlx240tff1156-1+7amba axi4 stream specificationsxc6vlx240t-ff1156-1xc6vlx240tff1156xc6slx45tfgg484xc6slx45tkintex 7amba axi designer user guide
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AMBA AXI verilog code
Abstract: BP130 verilog code for amba ahb master AMBA file write AXI verilog code CL013G AMBA AHB to AXI
Contextual Info: PrimeCell Infrastructure AMBA 3 AXI Register Slice BP130 Revision: r0p0 Technical Overview ™ This technical overview describes the functionality of the AXI register slice in the following sections: • Preliminary material on page 2 • About the AXI register slice on page 4
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bp130amba axi verilog codeverilog code for amba ahb masteramba file write axi verilog code+2cl013gamba ahb to axi
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AMBA AXI verilog code
Abstract: BP132 CL013G block diagram for asynchronous FIFO AMBA AXI Logic diagram for asynchronous FIFO awid ARM verilog code AMBA file write AXI verilog code
Contextual Info: PrimeCell Infrastructure AMBA 3 AXI Asynchronous Bridge BP132 Revision: r0p1 Technical Overview This technical overview describes the functionality of the AXI asynchronous bridge in the following sections: • Preliminary material on page 2 • About the AXI asynchronous bridge on page 3
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bp1320023bamba axi verilog codecl013g+6block diagram for asynchronous fifoamba axilogic diagram for asynchronous fifoawidarm verilog codeamba file write axi verilog code
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28F00AP30
Abstract: 28F00AP30TF IS61LVPS25636A XC6SL* MEMORY NUMONYX XILINX ipic axi DW10A emc core Spartan-6 FPGA
Contextual Info: LogiCORE IP AXI External Memory Controller v1.03a DS762 October 16, 2012 Product Specification Introduction LogiCORE IP Facts Table The AXI External Memory Controller EMC IP core provides a control interface for external synchronous, asynchronous SRAM, Flash and PSRAM/Cellular RAM
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ds762zynqtm-700028f00ap3028f00ap30tf+7is61lvps25636axc6sl* memorynumonyxxilinx ipic axidw10aemc corespartan-6 fpga
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XC6SLX16-2CSG324
Abstract: IPIF XC6SLX16-2 AMBA AXI designer user guide axi interrupt xilinx XC6VLX130T-1-FF1156 XPS ipic axi DS768 XILINX ipic axi XC7K410TFFG676-3
Contextual Info: LogiCORE IP AXI GPIO v1.01.b DS744 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The Xilinx LogiCORE IP Advanced eXtensible Interface General Purpose Input/Output (AXI GPIO) core provides a general purpose input/output interface
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ds74432-bitzynqtm-7000xc6slx16-2csg324+9ipifxc6slx16-2amba axi designer user guideaxi interrupt xilinxxc6vlx130t-1-ff1156xps ipic axids768xilinx ipic axixc7k410tffg676-3
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XC6VLX130T-1FF1156
Abstract: XILINX FIFO UART uart 19200 ise one stop bit XC6VLX130T-1-FF1156 FF1156 fgg484 Xilinx ISE Design Suite 14.2 XC7K410TFFG676-3 XC6VLX130T block diagram UART using VHDL
Contextual Info: LogiCORE IP AXI UART Lite v1.02a DS741 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Universal Asynchronous Receiver Transmitter (UART) Lite interface connects to the Advanced Microcontroller Bus Architecture
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ds741zynqtm-7000xc6vlx130t-1ff1156xilinx fifo uart+8uart 19200 ise one stop bitxc6vlx130t-1-ff1156ff1156fgg484xilinx ise design suite 14.2xc7k410tffg676-3xc6vlx130tblock diagram uart using vhdl
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