ASM5P2308A Search Results

ASM5P2308

Abstract: 2308A ASM5P2308A-1 ASM5P2308A-1H ASM5P2308A-2 ASM5P2308A-3 ASM5P2308A-4 ASM5P2308A-5H ASM5P2308A T5133
Contextual Info: ASM5P2308A November 2006 rev 1.5 3.3V Zero-Delay Buffer General Features • the Select Input Decoding Table. If all the output clocks are Zero input - output propagation delay, adjustable by capacitive load on FBK input. • Multiple configurations - Refer “ASM5P2308A

ASM5P2308A

Abstract: ASM5P2308A-1 ASM5P2308A-1H ASM5P2308A-2 ASM5P2308A-3 ASM5P2308A-4 ASM5P2308A-5H
Contextual Info: August 2004 ASM5P2308A rev 2.0 3.3V Zero-Delay Buffer which can be controlled by the select inputs as shown in General Features the Select Input Decoding Table. If all the output clocks are • Zero input - output propagation delay, adjustable by capacitive load on FBK input.

Contextual Info: ASM5P2308A October 2003 rev 1.0 3.3V Zero Delay Buffer General Features • Input Decoding Table. If all the output clocks are not required, Zero input - output propagation delay, adjustable by capacitive load on FBK input. • Multiple configurations - Refer “ASM5P2308A Configura-

S2S13

Contextual Info: ASM5P2308A 3.3V Zero-Delay Buffer General Features Zero input-output propagation delay, adjustable by capacitive load on FBK input Multiple configurations – Refer to ASM5P2308A Configurations Table Input frequency range: 10MHz to 133MHz Multiple low-skew outputs

ST TSSOP Marking

Abstract: 1t1t1
Contextual Info: ASM5P2308A March 2005 rev 1.3 3.3V Zero-Delay Buffer General Features • the Select Input Decoding Table. If all the output clocks are Zero input - output propagation delay, adjustable by also allows the input clock to be directly applied to the capacitive load on FBK input.

ASM5P2308A

Abstract: ASM5P2308A-1 ASM5P2308A-1H ASM5P2308A-2 ASM5P2308A-3 ASM5P2308A-4 ASM5P2308A-5H 5H 10
Contextual Info: ASM5P2308A September 2005 rev 1.4 3.3V Zero-Delay Buffer General Features • allows the input clock to be directly applied to the outputs Zero input - output propagation delay, adjustable by for chip and system testing purposes. capacitive load on FBK input.

P5P2308AF-1H16SR

Abstract: 1H16S
Contextual Info: ASM5P2308A 3.3 V Zero-Delay Buffer Description ASM5P2308A is a versatile, 3.3 V zero−delay buffer designed to distribute high−speed clocks. It is available in a 16−pin package. The part has an on−chip PLL which locks to an input clock presented on

ASM5P2308A

Abstract: ASM5P2308A-1 ASM5P2308A-1H ASM5P2308A-2 ASM5P2308A-3 ASM5P2308A-4 ASM5P2308A-5H
Contextual Info: November 2003 ASM5P2308A rev 1.1 3.3V Zero-Delay Buffer which can be controlled by the select inputs as shown in General Features the Select Input Decoding Table. If all the output clocks are • Zero input - output propagation delay, adjustable by capacitive load on FBK input.

1H08S

Abstract: PI6C2405A-1HW ASM706CUA SOIC-6 microchip ADM809RAR ADM705AN MAX809SEUR T ASM5P2309-1H-16-S K7N163601B MAX810JEUR
Contextual Info: Supervisors Cross Reference Guide Alliance Maxim/Dallas IMP ASM1232LP DS1232LPS-2 IMP1232LP ASM1232LPCMA DS1232LP IMP1232LPCMA ASM1232LPEMA DS1232LP IMP1232LPEMA ASM1232LPN DS1232LP IMP1232LPN Analog Devices Micrel Microchip MIC1232N TC1232CPA - - - - - -

Contextual Info: ASM5P23S08A November 2006 rev 1.5 3.3V ‘SpreadTrak’ Zero Delay Buffer General Features The ASM5P23S08A has two banks of four outputs each, • which can be controlled by the select inputs as shown in Zero input - output propagation delay, adjustable by

ADM809RAR

Abstract: AS7C256A hsbga 416 lcd cross reference IDT CYPRESS CROSS REFERENCE clocks DS1232* watch dog timer Product Selector Guide mbg* sot143 FS781 IDT74SSTV16857
Contextual Info: DISCLAIMER Alliance Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Alliance Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied